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| author | David Hendricks <dhendrix@chromium.org> | 2017-08-08 23:28:54 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-08-19 20:34:34 +0000 |
| commit | a1bccd88c3c8c0041795b96faef2cb4179bfbd7c (patch) | |
| tree | f7dd8abd576d25c606508fa2ea6b4007b5b3d291 | |
| parent | 4d440a7c4102faae21b16204e667ea74c1dc8e52 (diff) | |
| download | flashrom-a1bccd88c3c8c0041795b96faef2cb4179bfbd7c.tar.gz flashrom-a1bccd88c3c8c0041795b96faef2cb4179bfbd7c.tar.bz2 flashrom-a1bccd88c3c8c0041795b96faef2cb4179bfbd7c.zip | |
chipset_enable: Mark Braswell as tested
Reported by Uwe Vieweg:
https://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html
Change-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/20923
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 6a93d0d57..36e2838f4 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1740,7 +1740,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, - {0x8086, 0x229c, NT, "Intel", "Braswell", enable_flash_silvermont}, + {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont}, {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, |