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| author | Angel Pons <th3fanbus@gmail.com> | 2018-11-02 14:25:31 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-03 11:33:25 +0000 |
| commit | 7fb508dc137818587bf142ec1f28fbc1c3a371fc (patch) | |
| tree | 10d295db825b47c407d21f37e66bb4b7eff9e40a | |
| parent | f2cd32570eb8624c60e97aecd5c9045249b376fe (diff) | |
| download | flashrom-7fb508dc137818587bf142ec1f28fbc1c3a371fc.tar.gz flashrom-7fb508dc137818587bf142ec1f28fbc1c3a371fc.tar.bz2 flashrom-7fb508dc137818587bf142ec1f28fbc1c3a371fc.zip | |
chipset_enable.c: Mark Intel PM55 as DEP
Tested reading, writing and erasing the internal flash chip using an HP
Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since
all ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index c1639a6af..cbb88fd48 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1801,7 +1801,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, - {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, + {0x8086, 0x3b03, DEP, "Intel", "PM55", enable_flash_pch5}, {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5}, {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5}, {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, |