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authorDavid Hendricks <dhendrix@chromium.org>2010-08-26 21:27:17 -0700
committerNico Huber <nico.h@gmx.de>2019-09-24 18:49:09 +0000
commit15f539c8c978e002f2b6397a7a74e1af817d5cb3 (patch)
tree933422f889c4d668cace147b383c4aa3a9b024a6
parenta1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a (diff)
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ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE
This aligns the upstream master branch with chromium's. On-the-fly opcode reprogramming is supported by both branches so the default opcode shouldn't matter. Review URL: http://codereview.chromium.org/3239001 Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64 Signed-off-by: Mayur Panchal <panchalm@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--ichspi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ichspi.c b/ichspi.c
index 5a86c96fa..12ee126fb 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -324,7 +324,7 @@ static OPCODES O_ST_M25P = {
{
{JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
{JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
- {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
+ {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
{JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
{JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
{JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register