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| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-06 23:09:13 +0100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-12-18 10:59:23 +0000 |
| commit | 65067c7d8e3c0ea0ca0bd7101a036748a272dfb0 (patch) | |
| tree | 8cd9f7bfdad847854a9a5811ce0cd7103378fbdb | |
| parent | b76d281010886b4ddb2a5a6d36c3812a638a8abd (diff) | |
| download | flashrom-65067c7d8e3c0ea0ca0bd7101a036748a272dfb0.tar.gz flashrom-65067c7d8e3c0ea0ca0bd7101a036748a272dfb0.tar.bz2 flashrom-65067c7d8e3c0ea0ca0bd7101a036748a272dfb0.zip | |
chipset_enable.c: Mark Intel H110 as DEP
Tested reading, writing and erasing the internal flash chip using an HP
280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.
Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 9205d0e5e..040b151b0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2022,7 +2022,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, - {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, |