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| author | Angel Pons <th3fanbus@gmail.com> | 2020-04-15 12:59:42 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-04-17 00:28:19 +0000 |
| commit | aa4aa16554c2e9961147cabafc347fc22dbafdc0 (patch) | |
| tree | af632afb387523f07a2b416b9e127810ba1b6fa5 | |
| parent | e0fac2e4a655864c6c125e28918798502fe9651d (diff) | |
| download | flashrom-aa4aa16554c2e9961147cabafc347fc22dbafdc0.tar.gz flashrom-aa4aa16554c2e9961147cabafc347fc22dbafdc0.tar.bz2 flashrom-aa4aa16554c2e9961147cabafc347fc22dbafdc0.zip | |
chipset_enable.c: Disable SPI on ICH7 if booted from LPC
Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:
Error: SCIP never cleared!
To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.
Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.
Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
| -rw-r--r-- | chipset_enable.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 36d0dbe7f..783bb9426 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -757,6 +757,14 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera if (ret_fwh == ERROR_FATAL) return ret_fwh; + /* + * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted + * from LPC, the SCIP bit will never clear, which causes long delays and many error messages. + * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC. + */ + if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC)) + return 0; + /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ uint16_t spibar_offset; switch (ich_generation) { |