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| author | Mark Marshall <mark.marshall@csr.com> | 2010-12-03 14:48:11 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-12-03 14:48:11 +0000 |
| commit | 90021f28ff6cb97c53aeb18667addefb43c706e3 (patch) | |
| tree | 7ec04388c7b9dbb9796953d6616b855bf451d341 /Makefile | |
| parent | 859f3f0d751e92ec99c79408a4a7789bfb61a514 (diff) | |
| download | flashrom-90021f28ff6cb97c53aeb18667addefb43c706e3.tar.gz flashrom-90021f28ff6cb97c53aeb18667addefb43c706e3.tar.bz2 flashrom-90021f28ff6cb97c53aeb18667addefb43c706e3.zip | |
Add support for the Open Graphics Project development card, OGD1, as a SPI flash programmer
The project is in the the process of designing and making a complete,
open source, graphics card. More info at http://wiki.opengraphics.org.
The first development card is a PCI add in card containing a couple of
FPGAs and a couple of serial flash chips (amongst other things). The
FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its
own flash and does not need to be programmed by flashrom - it ensures
that the device can enumerate on the PCI bus without needing further
configuration.
The larger FPGA is the S3. This is configured from a large SPI flash
(2 MBytes). The second SPI flash is used to store the VGA BIOS. It is
smaller (128 KBytes). This patch adds support for programming either of
the two SPI flash chips.
The programmer device takes one configuration option which selects which
of the two flash chips is accessed. This must be set to either "cprom"
or "bprom". (The project refers to the two chips as "cprom" / "bprom",
"s3" and "bios" are more readable alternatives).
Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested
for write.
Corresponding to flashrom svn r1241.
Signed-off-by: Mark Marshall <mark.marshall@csr.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 13 |
1 files changed, 13 insertions, 0 deletions
@@ -146,6 +146,9 @@ CONFIG_NICNATSEMI ?= no # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable SPI on OGP cards for now. +CONFIG_OGP_SPI ?= yes + # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATE_SPI ?= yes @@ -165,10 +168,14 @@ else ifeq ($(CONFIG_NICINTEL_SPI), yes) override CONFIG_BITBANG_SPI = yes else +ifeq ($(CONFIG_OGP_SPI), yes) +override CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no endif endif endif +endif ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' @@ -258,6 +265,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_OGP_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' +PROGRAMMER_OBJS += ogp_spi.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_BUSPIRATE_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BUSPIRATE_SPI=1' PROGRAMMER_OBJS += buspirate_spi.o |