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author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-07-17 12:54:09 +0000 |
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committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-07-17 12:54:09 +0000 |
commit | 0d974e7a9263696fe3bfc7293bb0e632594e0925 (patch) | |
tree | ac83a822a78d0e27c96c9278943b8051107ec722 /bitbang_spi.c | |
parent | 1a854fc98ca68dae574a836ead8a6d3e6321fb18 (diff) | |
download | flashrom-0d974e7a9263696fe3bfc7293bb0e632594e0925.tar.gz flashrom-0d974e7a9263696fe3bfc7293bb0e632594e0925.tar.bz2 flashrom-0d974e7a9263696fe3bfc7293bb0e632594e0925.zip |
Refine SPI bitbanging
Change the SPI bitbanging core to fix a subtle bug (which had no
effect so far) and to make integration of the RayeR SPIPGM and Nvidia
MCP6x/MCP7x SPI patches easier. Kill a few global variables and require
explicit initialization of bitbanging delay.
A big to Johannes Sjölund for testing an earlier version of the code as
part of the Nvidia MCP6x/MCP7x SPI bitbanging patch.
Corresponding to flashrom svn r1085.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Diffstat (limited to 'bitbang_spi.c')
-rw-r--r-- | bitbang_spi.c | 31 |
1 files changed, 20 insertions, 11 deletions
diff --git a/bitbang_spi.c b/bitbang_spi.c index 6316a558c..b543fd457 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -26,46 +26,55 @@ #include "chipdrivers.h" #include "spi.h" -/* Length of half a clock period in usecs */ -int bitbang_spi_half_period = 0; +/* Length of half a clock period in usecs. */ +static int bitbang_spi_half_period; -enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; +static enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; -const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { +static const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { {}, /* This entry corresponds to BITBANG_SPI_INVALID. */ }; const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table); -void bitbang_spi_set_cs(int val) +/* Note that CS# is active low, so val=0 means the chip is active. */ +static void bitbang_spi_set_cs(int val) { bitbang_spi_master_table[bitbang_spi_master].set_cs(val); } -void bitbang_spi_set_sck(int val) +static void bitbang_spi_set_sck(int val) { bitbang_spi_master_table[bitbang_spi_master].set_sck(val); } -void bitbang_spi_set_mosi(int val) +static void bitbang_spi_set_mosi(int val) { bitbang_spi_master_table[bitbang_spi_master].set_mosi(val); } -int bitbang_spi_get_miso(void) +static int bitbang_spi_get_miso(void) { return bitbang_spi_master_table[bitbang_spi_master].get_miso(); } -int bitbang_spi_init(void) +int bitbang_spi_init(enum bitbang_spi_master master, int halfperiod) { + bitbang_spi_master = master; + bitbang_spi_half_period = halfperiod; + + if (bitbang_spi_master == BITBANG_SPI_INVALID) { + msg_perr("Invalid bitbang SPI master. \n" + "Please report a bug at flashrom@flashrom.org\n"); + return 1; + } bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); - buses_supported = CHIP_BUSTYPE_SPI; + bitbang_spi_set_mosi(0); return 0; } -uint8_t bitbang_spi_readwrite_byte(uint8_t val) +static uint8_t bitbang_spi_readwrite_byte(uint8_t val) { uint8_t ret = 0; int i; |