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| author | Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> | 2010-07-22 18:04:15 +0000 |
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| committer | Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> | 2010-07-22 18:04:15 +0000 |
| commit | a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6 (patch) | |
| tree | 9a784e968db73ec1e95bd27efe7aa3d7c7ca9a8e /cbtable.c | |
| parent | d97c0e02d610485357e569b2e1662d6bc6763d9e (diff) | |
| download | flashrom-a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6.tar.gz flashrom-a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6.tar.bz2 flashrom-a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6.zip | |
Move Intel SPI initialisation to ichspi.c
Smarter version could decide whether SPI is vital or not depending on
straps. Straps are currently implemented for ICH7. EP80579 is in the comment,
PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI".
Corresponding to flashrom svn r1098.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Diffstat (limited to 'cbtable.c')
0 files changed, 0 insertions, 0 deletions