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authorDanielZhang <danielzhang@mxic.com.cn>2024-04-12 15:44:10 +0800
committerAnastasia Klimchuk <aklm@chromium.org>2024-05-12 11:22:32 +0000
commitadeaaf6b5d6eaed9849faf0ec84532daa8940237 (patch)
tree28f96f81a199852217a7c85aee1528dbd448ec6a /flashchips.c
parent2638aafdbb0ceeefb271603f7396a9b80db074d9 (diff)
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flashchips: Add support for MXIC MX25R2035F
The MX25R2035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R2035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8696/MX25R2035F,%20Wide%20Range,%202Mb,%20v1.6.pdf Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64 Signed-off-by: DanielZhang <danielzhang@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'flashchips.c')
-rw-r--r--flashchips.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c
index 041ac404d..13024de94 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10334,6 +10334,53 @@ const struct flashchip flashchips[] = {
{
.vendor = "Macronix",
+ .name = "MX25R2035F",
+ .bustype = BUS_SPI,
+ .manufacture_id = MACRONIX_ID,
+ .model_id = MACRONIX_MX25R2035F,
+ .total_size = 256,
+ .page_size = 256,
+ /* OTP: 1024B total; enter 0xB1, exit 0xC1 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 64} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 8} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 4} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {1 * 256 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {1 * 256 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {1650, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {CONFIG, 3, OTP}
+ },
+
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "Macronix",
.name = "MX25R3235F",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,