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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-07-27 22:03:46 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2010-07-27 22:03:46 +0000 |
| commit | 1d3a2fefbc636fb569bd1d018fb97b1b17c08e99 (patch) | |
| tree | a384be3a9c9c890870117baf435a0312ecfd4a78 /gfxnvidia.c | |
| parent | 695fb5d0ac60c399fac4bac8595bfb8a0efdb30f (diff) | |
| download | flashrom-1d3a2fefbc636fb569bd1d018fb97b1b17c08e99.tar.gz flashrom-1d3a2fefbc636fb569bd1d018fb97b1b17c08e99.tar.bz2 flashrom-1d3a2fefbc636fb569bd1d018fb97b1b17c08e99.zip | |
Convert MMIO accesses of non-internal PCI-based programmers to be endian-agnostic
Convert all PCI-based external programmers to use special little-endian
accessors for all MMIO regions of PCI devices. This patch does _not_
touch the internal programmer (which is PCI-based as well).
Huge thanks go to Misha Manulis who worked with me to create a first
version of this patch for the satasii programmer based on modification
of generic code.
Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_
prefix for the abstraction layer.
NOTE to package maintainers: With this patch, compilation and usage of
flashrom should be safe on x86, x86_64, MIPS (little and big endian) and
PowerPC (big endian).
The internal programmer is disabled on non-x86/x86_64 (but it
compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi
can not be compiled on non-x86/x86_64 because port space I/O is
not (yet) supported. Please compile with default settings on
x86/x86_64 and with the following settings on all other architectures:
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no
CONFIG_RAYER_SPI=no
Corresponding to flashrom svn r1111.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
Diffstat (limited to 'gfxnvidia.c')
| -rw-r--r-- | gfxnvidia.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gfxnvidia.c b/gfxnvidia.c index 29e2910fa..252ddc5b3 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -100,10 +100,10 @@ int gfxnvidia_shutdown(void) void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } uint8_t gfxnvidia_chip_readb(const chipaddr addr) { - return mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } |