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| author | Nico Huber <nico.huber@secunet.com> | 2017-03-20 14:25:09 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-07-28 12:13:59 +0000 |
| commit | 93c306939b732fb05f6d8a692acc3fca78bc0f9f (patch) | |
| tree | 197478ba299562a8044c7d998c24e365af61b295 /programmer.h | |
| parent | d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6 (diff) | |
| download | flashrom-93c306939b732fb05f6d8a692acc3fca78bc0f9f.tar.gz flashrom-93c306939b732fb05f6d8a692acc3fca78bc0f9f.tar.bz2 flashrom-93c306939b732fb05f6d8a692acc3fca78bc0f9f.zip | |
chipset_enable: Add support for Intel Skylake / Kabylake
All publicly known Skylake / Kabylake / Sunrise Point PCH variants
share the same register interface [1..6]. Although all SPI configu-
ration is now done through the SPI PCI device 1f.5, we can't probe
for it directly since its PCI vendor and device IDs are usually hid-
den.
To work around the hidden IDs, we use another PCI accessor that doesn't
rely on the OS seeing the PCI device.
This handles SPI flashes only. While booting from LPC is still sup-
ported, it seems nobody uses it any more.
Some additional PCI IDs were gathered from driveridentifier.com.
TEST=Compiled with B150 set to NT (instead of BAD) and checked for
sane register readings.
[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform
Datasheet - Volume 1 of 2
Revision 002EN
Document Number 332995
[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms
Volume 2 of 2
Revision 001EN
Document Number 332996
[3] 7th Generation Intel® Processor Families I/O Platform
Datasheet - Volume 1 of 2
Revision 002
Document Number 334658
[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms
Datasheet - Volume 2 of 2
Revision 002
Document Number 334659
[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 004EN
Document Number 332690
[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 001EN
Document Number 332691
Change-Id: I000819aff25fbe9764f33df85f040093b82cd948
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18925
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Diffstat (limited to 'programmer.h')
| -rw-r--r-- | programmer.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/programmer.h b/programmer.h index fd9da9657..ec00bd9a9 100644 --- a/programmer.h +++ b/programmer.h @@ -650,6 +650,7 @@ enum ich_chipset { CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, CHIPSET_9_SERIES_WILDCAT_POINT_LP, + CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ }; /* ichspi.c */ |