Rework internal bus handling and laptop bail-out

We used to bail out on any unknown laptop. However, modern systems with
SPI flashes don't suffer from the original problem. Even if a flash chip
is shared with the EC, the latter has to expect the host to send regular
JEDEC SPI commands any time.

So instead of bailing out, we limit the set of buses to probe. If we
suspect to be running on a laptop, we only allow probing of SPI and
opaque programmers. The user can still use the existing force options
to probe all buses.

This will obsolete some board-enables that could be moved to `print.c`
in follow-up commits.

Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>

1 files changed, 1 insertions, 0 deletions

diff --git a/programmer.h b/programmer.h
index d22bc6b73..9da49f87c 100644
--- a/programmer.h
+++ b/programmer.h
@@ -226,6 +226,7 @@ int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
 struct penable {
 	uint16_t vendor_id;
 	uint16_t device_id;
+	enum chipbustype buses;
 	const enum test_state status;
 	const char *vendor_name;
 	const char *device_name;