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| author | Nico Huber <nico.h@gmx.de> | 2017-04-21 23:47:08 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-12-28 10:49:05 +0000 |
| commit | ed098d62d66d91cf7330a37f9b83e303eb7f56d8 (patch) | |
| tree | 639b6233e588fd8b4150b42112da36e239ba7fa4 /programmer.h | |
| parent | 7e3c81ae7122120fe10d43fcba61a513e2461de9 (diff) | |
| download | flashrom-ed098d62d66d91cf7330a37f9b83e303eb7f56d8.tar.gz flashrom-ed098d62d66d91cf7330a37f9b83e303eb7f56d8.tar.bz2 flashrom-ed098d62d66d91cf7330a37f9b83e303eb7f56d8.zip | |
spi: Move ICH BBAR quirk out of the way
Get rid of the layering violations around ICH's BBAR. Move all the weird
address handling into (surprise, surprise) `ichspi.c`. Might fix writes
for the `BBAR != 0` case by accident.
Background: Some ICHs have a BBAR (BIOS Base Address Configuration
Register) that, if set, limits the valid address range to [BBAR, 2^24).
Current code lifted addresses for REMS, RES and READ operations by BBAR,
now we do it for all addresses in ichspi. Special care has to be taken
if the BBAR is not aligned by the flash chip's size. In this case, the
lower part of the chip (from BBAR aligned down, up to BBAR) is inacces-
sible (this seems to be the original intend behind BBAR) and has to be
left out in the address offset calculation.
Change-Id: Icbac513c5339e8aff624870252133284ef85ab73
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22396
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'programmer.h')
| -rw-r--r-- | programmer.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/programmer.h b/programmer.h index a98b71359..b390a5331 100644 --- a/programmer.h +++ b/programmer.h @@ -661,7 +661,6 @@ enum ich_chipset { /* ichspi.c */ #if CONFIG_INTERNAL == 1 -extern uint32_t ichspi_bbar; int ich_init_spi(void *spibar, enum ich_chipset ich_generation); int via_init_spi(uint32_t mmio_base); |