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authorJason Wang <Qingpei.Wang@amd.com>2008-11-28 21:36:51 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-11-28 21:36:51 +0000
commita3f04be761d45aed2f6113eb2a6d08679370f546 (patch)
treeb1e437eb9e184676bc4ca62472bfb103ca4d2196 /spi.h
parent7f30022fb0fb62a484514e50d5b3f15157a5885d (diff)
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Add support for the AMD/ATI SB600 southbridge SPI functionality
This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'spi.h')
-rw-r--r--spi.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/spi.h b/spi.h
index c096dce5c..25ce29774 100644
--- a/spi.h
+++ b/spi.h
@@ -80,6 +80,11 @@
#define JEDEC_RDSR_INSIZE 0x01
#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
+/* Write Status Enable */
+#define JEDEC_EWSR 0x50
+#define JEDEC_EWSR_OUTSIZE 0x01
+#define JEDEC_EWSR_INSIZE 0x00
+
/* Write Status Register */
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02