Revert "flashchips: port S25FS(128S) chip from chromiumos"

This reverts commit a3519561bd0fb44153bb376322b799000657576f.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 0 insertions, 86 deletions

diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 083a832f5..4b9b2a9b8 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -108,89 +108,6 @@ uint8_t spi_read_status_register(const struct flashctx *flash)
 	return readarr[0];
 }
 
-static int spi_restore_status(struct flashctx *flash, uint8_t status)
-{
-	msg_cdbg("restoring chip status (0x%02x)\n", status);
-	return spi_write_status_register(flash, status);
-}
-
-/* 'Read Any Register' used on Spansion/Cypress S25FS chips */
-int s25fs_read_cr(struct flashctx *const flash, uint32_t addr)
-{
-	int result;
-	uint8_t cfg;
-	/* By default, 8 dummy cycles are necessary for variable-latency
-	   commands such as RDAR (see CR2NV[3:0]). */
-	unsigned char read_cr_cmd[] = {
-					CMD_RDAR,
-					(addr >> 16) & 0xff,
-					(addr >> 8) & 0xff,
-					(addr & 0xff),
-					0x00, 0x00, 0x00, 0x00,
-					0x00, 0x00, 0x00, 0x00,
-	};
-
-	result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg);
-	if (result) {
-		msg_cerr("%s failed during command execution at address 0x%x\n",
-			__func__, addr);
-		return -1;
-	}
-
-	return cfg;
-}
-
-/* 'Write Any Register' used on Spansion/Cypress S25FS chips */
-int s25fs_write_cr(struct flashctx *const flash,
-			  uint32_t addr, uint8_t data)
-{
-	int result;
-	struct spi_command cmds[] = {
-	{
-		.writecnt	= JEDEC_WREN_OUTSIZE,
-		.writearr	= (const unsigned char[]){ JEDEC_WREN },
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= CMD_WRAR_LEN,
-		.writearr	= (const unsigned char[]){
-					CMD_WRAR,
-					(addr >> 16) & 0xff,
-					(addr >> 8) & 0xff,
-					(addr & 0xff),
-					data
-				},
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 0,
-		.writearr	= NULL,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}};
-
-	result = spi_send_multicommand(flash, cmds);
-	if (result) {
-		msg_cerr("%s failed during command execution at address 0x%x\n",
-			__func__, addr);
-		return -1;
-	}
-
-	programmer_delay(T_W);
-	return spi_poll_wip(flash, 1000 * 10);
-}
-
-/* Used on Spansion/Cypress S25FS chips */
-int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg)
-{
-	int ret = 0;
-
-	msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg);
-	ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg);
-	ret |= s25fs_software_reset(flash);
-	return ret;
-}
-
 /* A generic block protection disable.
  * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise.
  * Tests if the register bits are locked with the lock_mask (lock_mask).
@@ -222,9 +139,6 @@ static int spi_disable_blockprotect_generic(struct flashctx *flash, uint8_t bp_m
 		return 0;
 	}
 
-	/* restore status register content upon exit */
-	register_chip_restore(spi_restore_status, flash, status);
-
 	msg_cdbg("Some block protection in effect, disabling... ");
 	if ((status & lock_mask) != 0) {
 		msg_cdbg("\n\tNeed to disable the register lock first... ");