diff options
| -rw-r--r-- | board_enable.c | 8 | ||||
| -rw-r--r-- | buspirate_spi.c | 2 | ||||
| -rw-r--r-- | cbtable.c | 2 | ||||
| -rw-r--r-- | chipset_enable.c | 2 | ||||
| -rw-r--r-- | coreboot_tables.h | 8 | ||||
| -rw-r--r-- | dediprog.c | 4 | ||||
| -rw-r--r-- | flashchips.c | 4 | ||||
| -rw-r--r-- | flashchips.h | 2 | ||||
| -rw-r--r-- | ichspi.c | 4 | ||||
| -rw-r--r-- | it85spi.c | 2 | ||||
| -rw-r--r-- | jedec.c | 2 | ||||
| -rw-r--r-- | nicintel.c | 2 | ||||
| -rw-r--r-- | pcidev.c | 4 | ||||
| -rw-r--r-- | serprog.c | 2 | ||||
| -rw-r--r-- | udelay.c | 4 |
15 files changed, 26 insertions, 26 deletions
diff --git a/board_enable.c b/board_enable.c index 182a4551f..a3e451509 100644 --- a/board_enable.c +++ b/board_enable.c @@ -159,7 +159,7 @@ struct winbond_mux { struct winbond_port { const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ uint8_t ldn; /* LDN this GPIO register is located in */ - uint8_t enable_bit; /* bit in 0x30 of that LDN to enable + uint8_t enable_bit; /* bit in 0x30 of that LDN to enable the GPIO port */ uint8_t base; /* base register in that LDN for the port */ }; @@ -547,8 +547,8 @@ void w83697xx_memw_enable(uint16_t port) } } else { msg_pinfo("BIOS ROM is disabled\n"); - } - w836xx_ext_leave(port); + } + w836xx_ext_leave(port); } /* @@ -1036,7 +1036,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are - easily told apart from each other by the class of the + easily told apart from each other by the class of the LPC bridge, but have the same SMBus bridge IDs */ if (dev->func != 0) { msg_perr("MCP LPC bridge at unexpected function" diff --git a/buspirate_spi.c b/buspirate_spi.c index f82541552..00a4423e8 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -42,7 +42,7 @@ static int buspirate_serialport_setup(char *dev) { /* 115200bps, 8 databits, no parity, 1 stopbit */ sp_fd = sp_openserport(dev, BP_DEFAULTBAUD); - if (sp_fd == SER_INV_FD) + if (sp_fd == SER_INV_FD) return 1; return 0; } @@ -289,7 +289,7 @@ int cb_parse_table(const char **vendor, const char **model) } addr = ((char *)lb_table) - ((char *)table_area) + start; - msg_pinfo("coreboot table found at 0x%lx.\n", + msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); diff --git a/chipset_enable.c b/chipset_enable.c index 8243455b4..9c88695f1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1117,7 +1117,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) /* * Geode systems write protect the BIOS via RCONFs (cache settings similar - * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. + * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. * * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. * To enable write to NOR Boot flash for the benefit of systems that have such diff --git a/coreboot_tables.h b/coreboot_tables.h index 2e9652670..a5f1586fd 100644 --- a/coreboot_tables.h +++ b/coreboot_tables.h @@ -29,7 +29,7 @@ * is expected to be information that cannot be discovered by * other means, such as querying the hardware directly. * - * All of the information should be Position Independent Data. + * All of the information should be Position Independent Data. * That is it should be safe to relocated any of the information * without it's meaning/correctness changing. For table that * can reasonably be used on multiple architectures the data @@ -52,9 +52,9 @@ * table entries and be backwards compatible, but it is not required. */ -/* Since coreboot is usually compiled 32bit, gcc will align 64bit - * types to 32bit boundaries. If the coreboot table is dumped on a - * 64bit system, a uint64_t would be aligned to 64bit boundaries, +/* Since coreboot is usually compiled 32bit, gcc will align 64bit + * types to 32bit boundaries. If the coreboot table is dumped on a + * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * * lb_uint64 will keep 64bit coreboot table values aligned to 32bit diff --git a/dediprog.c b/dediprog.c index 146b3e7d6..c4d5c9ddd 100644 --- a/dediprog.c +++ b/dediprog.c @@ -505,8 +505,8 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned if (!transfers[i]) { msg_perr("Allocating libusb transfer %i failed: %s!\n", i, libusb_error_name(ret)); goto err_free; - } - } + } + } /* Now transfer requested chunks using libusb's asynchronous interface. */ while (!status.error && (status.queued_idx < count)) { diff --git a/flashchips.c b/flashchips.c index 70057d490..98a41a9d0 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3068,7 +3068,7 @@ const struct flashchip flashchips[] = { } }, .printlock = printlock_at49f, - .write = write_jedec_1, + .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, }, @@ -13833,7 +13833,7 @@ const struct flashchip flashchips[] = { .name = "SST49LF080A", .bustype = BUS_LPC, /* A/A Mux */ .manufacture_id = SST_ID, - .model_id = SST_SST49LF080A, + .model_id = SST_SST49LF080A, .total_size = 1024, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, diff --git a/flashchips.h b/flashchips.h index 68a67faa6..c4ea6366d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -592,7 +592,7 @@ #define PMC_PM49FL002 0x6D #define PMC_PM49FL004 0x6E -/* +/* * The Sanyo chip found so far uses SPI, first byte is manufacture code, * second byte is the device code, * third byte is a dummy byte. @@ -712,7 +712,7 @@ static void ich_set_bbar(uint32_t min_addr) bbar_off = ICH9_REG_BBAR; break; } - + ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", @@ -737,7 +737,7 @@ static void ich_set_bbar(uint32_t min_addr) * may even crash. */ static void ich_read_data(uint8_t *data, int len, int reg0_off) - { +{ int i; uint32_t temp32 = 0; @@ -54,7 +54,7 @@ /* The 8042 keyboard controller uses an input buffer and an output buffer to * communicate with the host CPU. Both buffers are 1-byte depth. That means - * IBF is set to 1 when the host CPU sends a command to the input buffer + * IBF is set to 1 when the host CPU sends a command to the input buffer * of the EC. IBF is cleared to 0 once the command is read by the EC. */ #define KB_IBF (1 << 1) /* Input Buffer Full */ @@ -68,7 +68,7 @@ void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst) * The Winbond W39V040C wants 50 ms between reads on sector erase toggle, * but experiments show that 2 ms are already enough. Pick a safety factor * of 4 and use an 8 ms delay. - * Given that erase is slow on all chips, it is recommended to use + * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst) diff --git a/nicintel.c b/nicintel.c index 69b40d34b..b2fe82a23 100644 --- a/nicintel.c +++ b/nicintel.c @@ -40,7 +40,7 @@ const struct dev_entry nics_intel[] = { #define NICINTEL_MEMMAP_SIZE (128 * 1024) #define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1) -#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10 +#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10 #define CSR_FCR 0x0c @@ -325,13 +325,13 @@ int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data) register_undo_pci_write_byte(dev, reg); return pci_write_byte(dev, reg, data); } - + int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data) { register_undo_pci_write_word(dev, reg); return pci_write_word(dev, reg, data); } - + int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data) { register_undo_pci_write_long(dev, reg); @@ -662,7 +662,7 @@ int serprog_init(void) } msg_pdbg(MSGHEADER "operation buffer size is %d\n", sp_device_opbuf_size); - } + } if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { uint8_t en = 1; @@ -170,7 +170,7 @@ recalibrate: /* Avoid division by zero, but in that case the loop is shot anyway. */ if (!timeusec) timeusec = 1; - + /* Compute rounded up number of loops per microsecond. */ micro = (count * micro) / timeusec + 1; msg_pdbg("%luM loops per second, ", micro); @@ -183,7 +183,7 @@ recalibrate: for (i = 0; i < 4; i++) { if (resolution && (resolution < 10)) { timeusec = measure_delay(100); - } else if (resolution && + } else if (resolution && (resolution < ULONG_MAX / 200)) { timeusec = measure_delay(resolution * 10) * 100 / (resolution * 10); |