diff options
Diffstat (limited to 'hwaccess.c')
-rw-r--r-- | hwaccess.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/hwaccess.c b/hwaccess.c index 830013ea9..44d787146 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -26,6 +26,15 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +/* sync primitive is not needed because x86 uses uncached accesses + * which have a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +63,68 @@ void release_io_perms(void) #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses + * in mode 2 which has a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +141,33 @@ uint32_t mmio_readl(void *addr) { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} |