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-rw-r--r--ich_descriptors.c37
1 files changed, 22 insertions, 15 deletions
diff --git a/ich_descriptors.c b/ich_descriptors.c
index a12022c6c..1fc8835ea 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -824,6 +824,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
case CHIPSET_8_SERIES_WELLSBURG:
case CHIPSET_9_SERIES_WILDCAT_POINT:
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
+ case CHIPSET_100_SERIES_SUNRISE_POINT:
if (idx == 0) {
size_enc = desc->component.dens_new.comp1_density;
} else {
@@ -849,16 +850,22 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
/* Only used by ichspi.c */
#if CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))
-static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar)
+static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16_t offset, void *spibar)
{
uint32_t control = 0;
control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS;
control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI;
- mmio_le_writel(control, spibar + ICH9_REG_FDOC);
- return mmio_le_readl(spibar + ICH9_REG_FDOD);
+ if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) {
+ mmio_le_writel(control, spibar + PCH100_REG_FDOC);
+ return mmio_le_readl(spibar + PCH100_REG_FDOD);
+ } else {
+ mmio_le_writel(control, spibar + ICH9_REG_FDOC);
+ return mmio_le_readl(spibar + ICH9_REG_FDOD);
+ }
+
}
-int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
+int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc)
{
uint8_t i;
uint8_t nr;
@@ -888,15 +895,15 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD...");
/* content section */
- desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar);
- desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar);
- desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar);
- desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar);
+ desc->content.FLVALSIG = read_descriptor_reg(cs, 0, 0, spibar);
+ desc->content.FLMAP0 = read_descriptor_reg(cs, 0, 1, spibar);
+ desc->content.FLMAP1 = read_descriptor_reg(cs, 0, 2, spibar);
+ desc->content.FLMAP2 = read_descriptor_reg(cs, 0, 3, spibar);
/* component section */
- desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar);
- desc->component.FLILL = read_descriptor_reg(1, 1, spibar);
- desc->component.FLPB = read_descriptor_reg(1, 2, spibar);
+ desc->component.FLCOMP = read_descriptor_reg(cs, 1, 0, spibar);
+ desc->component.FLILL = read_descriptor_reg(cs, 1, 1, spibar);
+ desc->component.FLPB = read_descriptor_reg(cs, 1, 2, spibar);
/* region section */
nr = desc->content.NR + 1;
@@ -906,12 +913,12 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc)
return ICH_RET_ERR;
}
for (i = 0; i < 5; i++)
- desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar);
+ desc->region.FLREGs[i] = read_descriptor_reg(cs, 2, i, spibar);
/* master section */
- desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar);
- desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar);
- desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar);
+ desc->master.FLMSTR1 = read_descriptor_reg(cs, 3, 0, spibar);
+ desc->master.FLMSTR2 = read_descriptor_reg(cs, 3, 1, spibar);
+ desc->master.FLMSTR3 = read_descriptor_reg(cs, 3, 2, spibar);
/* Accessing the strap section via FDOC/D is only possible on ICH8 and
* reading the upper map is impossible on all chipsets, so don't bother.