diff options
Diffstat (limited to 'spi25_statusreg.c')
| -rw-r--r-- | spi25_statusreg.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c index d0ce8597a..2859b2320 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -100,6 +100,13 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot write SR3: unsupported by chip\n"); return 1; + case SECURITY: + /* + * Security register doesn't have a normal write operation. Instead, + * there are separate commands that set individual OTP bits. + */ + msg_cerr("Cannot write SECURITY: unsupported by design\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -195,6 +202,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot read SR3: unsupported by chip\n"); return 1; + case SECURITY: + if (feature_bits & FEATURE_SCUR) { + read_cmd = JEDEC_RDSCUR; + break; + } + msg_cerr("Cannot read SECURITY: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; |