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* ichspi: Unify timeouts across all SPI operations to 30sv1.1.1-rc1v1.1.11.1.xSubrata Banik2022-10-301-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: This patch was backported from the master branch and it was modified so that it can be applied on the 1.1.x branch. `ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument in favor of a fixed timeout of `30 seconds` for any given SPI operation as recommended by the SPI programming guide. Document: Alder Lake-P Client Platform SPI Programming Guide Rev 1.30 (supporting document for multi-master accessing the SPI Flash device.) Refer to below section to understand the problem in more detail and SPI operation timeout recommendation from Intel in multi-master scenarios. On Intel Chipsets that support multi-mastering access of the SPI flash may run into a timeout failure when the operation initiated from a single master just follows the SPI operational timeout recommendation as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR specification, table 9.7). In the multi-master SPI accessing scenario using hardware sequencing operation, it's impossible to know the actual status of the SPI bus prior to individual master starting the operation (SPI Cycle In Progress a.k.a SCIP bit represents the status of SPI operation on individual master). Thus, any SPI operation triggered in multi-master environment might need to account a worst case scenario where the most time consuming operation might have occupied the SPI bus from a master and an operation initiated by another master just timed out. Here is the timeout calculation for any hardware sequencing operation: Worst Case Operational Delay = (Maximum Time consumed by a SPI operation + Any marginal adjustment) Timeout Recommendation for Hardware Sequencing Operation = ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + Current Operational latency) Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC, GbE and other reserved etc, hence, the Timeout Calculation for SPI erase Operation would look like as below: Maximum Time consumed by a SPI Operation = 5 seconds Worst Case Operational Delay = 5 seconds Timeout Recommendation for Hardware Seq Operation = 5 seconds * (6 - 1) + 5 seconds = 30 seconds BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Original-Signed-off-by: Subrata Banik <subratabanik@google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Makefile: Fix dependencies for developerbox_spiFelix Singer2022-10-062-1/+5
| | | | | | | | | | | | | | | | Note: This patch was backported from the master branch and it was modified so that it can be applied on the 1.1.x branch. The developerbox_spi programmer depends on bitbang SPI support. Thus, fix that. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ic0fe589ffdccede0fbf6360c2bebe58a36654f10 Reviewed-on: https://review.coreboot.org/c/flashrom/+/66096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68011
* Replace freenode referencesAngel Pons2022-10-063-31/+16
| | | | | | | | | | | | | The flashrom project no longer uses freenode. To avoid having outdated man pages in the future, the contact methods are now listed in the wiki. Change-Id: I75e8f43c50dc4c3feede0250334a877cdaac8103 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68061
* print_wiki.c: Update mailing list referenceAngel Pons2022-10-061-1/+1
| | | | | | | | | | Change-Id: I5c67b5b3be2f306132d8565539bbf10477222026 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68060
* pcidev: Always fetch ident infoNico Huber2022-09-292-6/+17
| | | | | | | | | | | | | | | | | | | | As discovered earlier[1], the `vendor_id` and `device_id` fields are not always automatically set. However, we use these fields throughout flash- rom. To not lose track when we actually fetched them, let's always call pci_fill_info(PCI_FILL_IDENT) before returning a `pci_dev` handle. [1] Commit ca2e3bce0 (pcidev.c: populate IDs with pci_fill_info()) Backported to older versions where pcidev handling was much more scattered. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iae2511178bec44343cbe902722fdca9eda036059 Ticket: https://ticket.coreboot.org/issues/367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64573 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* pcidev.c: populate IDs with pci_fill_info()Daniel Verkamp2022-09-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With pciutils 3.7.0, flashrom is unable to match any PCI devices by vendor/device ID because the vendor_id and device_id fields of struct pci_dev are not filled in. Call pci_fill_info() to request these identifiers before trying to match them against the supported device list. The pciutils ChangeLog for 3.7.0 mentions that the documentation and back-end behavior for pci_fill_info() was updated; it seems that a call to pci_fill_info() was always intended to be required, but some backends (such as the sysfs one used on Linux) would fill the identifier fields even when not requested by the user. The pci_fill_info() function and the PCI_FILL_IDENT flag have been available for all versions of pciutils since at least 2.0 from 1999, so it should be safe to add without any version checks. With this change, reading/writing a nicintel_spi boot ROM is successful. Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Change-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef Reviewed-on: https://review.coreboot.org/c/flashrom/+/46310 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67858 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* linux_mtd: check ioctl() return value properlyNikolai Artemiev2022-09-291-3/+5
| | | | | | | | | | | | | | | | | | Make the linux_mtd driver treat any negative return value from the MEMERASE ioctl as an error. Previously it only treated -1 as an error. BUG=b:213561594,b:210973586,b:182223106 BRANCH=none TEST=builds Change-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67857 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.8: add missing entry for `--flash-contents`Michael Niewöhner2022-09-291-0/+7
| | | | | | | | | | Change-Id: I64a8200a86329bd26a2069c5dc39430de9f8ba09 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67856 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* jlink_spi: Reduce transfer sizeMarc Schink2022-09-291-1/+1
| | | | | | | | | | | | | | The maximum transfer size is too large for some devices and results in an USB timeout. Change-Id: If2c00b1524ec56740bdfe290096c3546cf375d73 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67855 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* linux_mtd: Disable buffering on the mtd deviceDouglas Anderson2022-09-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We open the device node for the MTD device with this: dev_fp = fopen(dev_path, "r+") In C fopen() is allowed to provide _buffered_ access to the file. That means that the standard library is allowed to read ahead and/or return cached data. That's really not what we want for something like this. Let's turn it off. This fixes a problem where flashrom would sometimes fail to "verify" that it erased the flash. The error message would look something like this: Erasing and writing flash chip... FAILED at 0x0000e220! Expected=0xff, Found=0xe9, failed byte count from 0x0000e200-0x0000e2ff: 0xdc failed byte count from 0x0000e000-0x0000efff: 0xffffffff ERASE_FAILED FAILED! Uh oh. Erase/write failed. Checking if anything changed. After the failure I could read the flash device with a new invocation of flashrom and I would see that, indeed, the erase had worked. Tracing in the kernel showed that when the failure happened we saw a pattern that looked like this: * Read 0x0b00 bytes starting at 0x0000d000 * Read 0x1000 bytes starting at 0x0000db00 * Erase 0x1000 bytes starting at 0x0000e000 ...and then there was _not_ a read after the erase. It can be assumed that, since userspace had already read 0xdb00 - 0xeaff that it was looking at old buffered data after the erase. Signed-off-by: Douglas Anderson <dianders@chromium.org> Change-Id: I989afd83a33013b2756a0090d6b08245613215c6 Reviewed-on: https://review.coreboot.org/c/flashrom/+/50155 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67854 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* chipset_enable.c: Validate physmap() return rcrb valueEdward O'Callaghan2022-09-291-0/+2
| | | | | | | | | | | | | Validate the physical mapping in enable_flash_silvermont(). Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67853 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2022-09-291-0/+2
| | | | | | | | | | | | | Port from the ChromiumOS fork of flashrom. Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67852 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* it87spi.c: Prevent use-after-free bugAngel Pons2022-09-291-1/+2
| | | | | | | | | | | | | | The memory for the `param` string is aliased by `dualbiosindex_suffix`. Moreover, `errno` could have been modified by the call to `free()`. Therefore, only free the former when there are no more uses of either. Change-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67851 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* spi25: Debug flashrom crash when Write Protect is ONYuji Sasaki2022-09-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hardware write protect is applied, flashrom crashed and generate coredump. spi_disable_blockprotect_generic() calls flash->chip->printlock() method when disable was failed, but this method is optional, can be NULL depends on type of flashrom chip. NULL pointer check before call is added to avoid crash. BRANCH=none BUG=b:129083894 TEST=Run on Mistral P2 (On CR50 console, run "wp disable") flashrom --wp-range 0 0x400000 flashrom --wp-enable (On CR50 console, run "wp enable") flashrom -r /tmp/test.bin Verify "Block protection could not be disabled!" is shown, but flash read completes. Signed-off-by: Yuji Sasaki <sasakiy@chromium.org> Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e Reviewed-on: https://chromium-review.googlesource.com/1535140 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67850 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* dummyflasher: Add error check for file readJacob Garber2022-09-291-2/+6
| | | | | | | | | | | | | | Print an error message and return if the read from emu_persistent_image fails. Change-Id: Icd1a72f9171e547f2081ba4bc53834a17ef7fcab Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403912 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67849 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* linux_spi: Use fgets() to read buffer sizeJacob Garber2022-09-291-2/+1
| | | | | | | | | | | | | | | | | Since fread() returns the number of bytes read, this currently will only check for errors if it returns 0 (i.e. the file was empty). However, it is possible for fread() to encounter an error after reading a few bytes, which this doesn't catch. Fix this by using fgets() instead, which will return NULL if EOF or an error is encountered, and is simpler anyway. Change-Id: I4f37c70e97149b87c6344e63a57d11ddde7638c4 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403824 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67848 Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashchips: Fix N25Q512 bulk eraseJacob Creedon2022-09-291-2/+2
| | | | | | | | | | | | | | The N25Q is a stacked device, so it requires 0xC4 to perform a die erase. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67847 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* pickit2_spi: Fix "dead" assignmentElyes HAOUAS2022-09-291-1/+7
| | | | | | | | | | | | | | | | | | We never read the first 'ret'. Let's check the first 'ret' and exit if it failed. Also, print the version only when the command succeeded. Backported to libusb-v0 version (checking for CMD_LENGTH instead of 0 return value). Found-by: scan-build 7.0.1-8 Change-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34403 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* dmi: Correctly check for ERROR_PTRNico Huber2022-03-071-1/+1
| | | | | | | | | | | | | | For the physmap*() functions, NULL is considered valid return value. Fixes a segmentation fault when DMI tables can't be mapped. Tested on intel/eblake board with broken coreboot. Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Make internal variables staticJacob Garber2022-03-0710-18/+18
| | | | | | | | | | | | | | | | All these variables are only used in the files they are defined in, so they can be made static. (Backported as it untangles aliased global objects.) Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62612 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* test_build.sh: Move build test procedure to repositoryPatrick Georgi2022-03-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git (Backported minus the Meson support) Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62617 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Nico Huber <nico.h@gmx.de>
* libflashrom: Add CPP guard to fix big-endian buildsv1.1Nico Huber2019-06-091-0/+2
| | | | | | | | | | | Calm a compiler warning on big-endian builds about the unused static flashrom_layout_parse_fmap(). The guard is ugly but gets the job done. We should forbid endian-specific code in the future, I guess. Change-Id: Id3f4a57e027f88cc469ed50312adddcc8af71a63 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33297 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: Also blacklist J-Link SPI for DOSNico Huber2019-06-081-0/+6
| | | | | | | | | | | | | libjaylink will probably never be available. Change-Id: Ie9222f82e16fe4c76fe7dd0f9aac7de6a862ab98 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marc Schink <flashrom-dev@marcschink.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: Blacklist Digilent SPI (using USB) for DOSNico Huber2019-06-081-1/+6
| | | | | | | | | Change-Id: I9a7dd5a2afcd12dd247e1f5534db61b79d77525e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* usbdev: Only match requested USB devicesv1.1-rc2Patrick Rudolph2019-06-031-1/+1
| | | | | | | | | | | | | Don't use a device that has the same vendor ID, but a different than requested product ID. Fixes broken dediprog detection with TOMU in use. Change-Id: I08c1c363ce2d6603e46efecc61d3910e02314fca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32892 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog: Disable 4BA completelyv1.1-rc1Nico Huber2019-04-023-0/+18
| | | | | | | | | | | This is an interim solution. We'll have to enable 4BA step-by-step for each dediprog protocol version. Change-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Fix verification with sparse layoutsNico Huber2019-04-023-9/+34
| | | | | | | | | | | | The full verification step was not accounting for sparse layouts. Instead of the old contents, combine_image_by_layout() implicitly assumed the new contents for unspecified regions. Change-Id: I44e0cea621f2a3d4dc70fa7e93c52ed95e54014a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Remove trailing whitespaceElyes HAOUAS2019-03-048-16/+16
| | | | | | | | | Change-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout.c: Remove unused variableArthur Heymans2019-03-041-2/+0
| | | | | | | | | Change-Id: I0c0c085999a12987376d75825fcf43e788a55a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout: Add missing stdbool.h includeNico Huber2019-03-041-0/+1
| | | | | | | | | | Change-Id: I9a413d491038b29c832011a738f3b49e029dcf6f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Fix erasing of unaligned regionsNico Huber2019-03-041-3/+66
| | | | | | | | | | | | | | | | | | The erase (-E) feature is somehow a brute force method, but still, if we are given a region to erase, we should make sure to restore surrounding data if the erase block expands beyond the region. It shares a lot of code with the write path. Though, experiments with common functions have shown that it would make the whole function even harder to read. Maybe we could add some abstraction if we ever need similar code on a third path. Change-Id: I5fc35310f0b090f218cd1d660e27fb39dd05c3c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Fix several -Wno-implicit-fallthrough warningsRichard Hughes2019-02-114-3/+9
| | | | | | | | | | | | GCC is picky about the comment being where the break should go. Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix one more -Wmissing-field-initializers warningRichard Hughes2019-02-031-1/+3
| | | | | | | | | | | | | Fixes: ichspi.c: In function ‘ich_init_spi’: ichspi.c:1707:9: warning: missing initializer for field ‘component’ Change-Id: Iee5728167963fece24822ad2e3ab7bd9d444b42c Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/31224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix a trivial calloc warningRichard Hughes2019-02-031-1/+1
| | | | | | | | Change-Id: Id457c15555a6ca6333474601f92982446afa40ab Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/31223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wno-missing-field-initializers warningsRichard Hughes2019-02-033-2/+8
| | | | | | | | Change-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wold-style-declaration warningsRichard Hughes2019-02-034-5/+5
| | | | | | | | Change-Id: Iffe5e652779a13ee7f64696fb5df4a781fe9a632 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* buspirate_spi: Fix a missing error check during _init()Richard Hughes2019-01-051-0/+2
| | | | | | | | Change-Id: I17c6737853bf311b3f7aa9bfb10b54ce19e95ecc Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix a tiny memory leak in the CLI toolRichard Hughes2019-01-051-0/+1
| | | | | | | | Change-Id: Iec696cb15dcf437f08e1e4f2a5a1faa0df6fd081 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add initial J-Link SPI programmerMarc Schink2019-01-056-1/+592
| | | | | | | | | | Tested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V. Change-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e Signed-off-by: Marc Schink <flashrom-dev@marcschink.de> Reviewed-on: https://review.coreboot.org/c/28087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* linux_spi: Hardcode default spispeed of 2MHzNico Huber2018-12-221-10/+13
| | | | | | | | | | | | Leaving the `linux_spi` driver's unknown default is almost never what we want and resulted in many support requests since Raspbian switched to a default that is too high for most applications. Change-Id: I9361b7c1a1ab8900a619b06e1dae14cd87eb56c2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* chipset_enable.c: Mark Intel C224 as DEPTristan Corrick2018-12-221-1/+1
| | | | | | | | | | | | Tested on a Supermicro X10SLM+-F. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libflashrom.h: Add missing includesNico Huber2018-12-211-0/+2
| | | | | | | | | | <stddef.h> for `size_t` and <sys/types.h> for `off_t`. Change-Id: Ifc84dfe2a06633321d0abd364bdea1216925a779 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* fmap: Fix length calculation in error messageNico Huber2018-12-211-1/+1
| | | | | | | | Change-Id: Ie0f448970de6a7829f304448e0835eaeb7d103a3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog: Fix small, unaligned readsNico Huber2018-12-061-4/+4
| | | | | | | | | | | | | | | This never was a use case until now but the `--fmap` code makes it obvious: Unaligned reads that were smaller than the `chunksize` here, were extended without considering the length of the buffer read into. With that fixed we run into the next problem: dediprog_spi_bulk_read() shouldn't report an error when an empty read is unaligned. Change-Id: Ie12b62499ebfdb467d5126c00d327c76077ddead Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable.c: Mark Intel PM55 as DEPAngel Pons2018-11-031-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Sanyo LE25FU206/A and LE25FU106BAngel Pons2018-11-012-0/+103
| | | | | | | | | | | As per user `The_Raven Raven` on the mailing list. Since the added values had some inconsistencies, the chips are marked as untested. Change-Id: I6c26aafdca232110986334e85297d73d513600dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel H81 as DEPTristan Corrick2018-11-011-1/+1
| | | | | | | | | | | | Tested on an ASRock H81M-HDS. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add IS25LP256 and IS25WP256David Hendricks2018-10-302-0/+102
| | | | | | | | | | | Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q256JV supportDavid Hendricks2018-10-292-1/+49
| | | | | | | | | | | | | | Similar to W25Q256FV, but it supports the native 4BA page program instruction (12h). Note that the variant with QE enabled by default shares the device ID of the W25Q256FV. Tested using a Raspberry Pi. Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* dmi: Remove nonsense guard; Makefile handles itNico Huber2018-10-231-4/+0
| | | | | | | | Change-Id: If4216be1f9ed308e4580c36d0356480e637ffc82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-07 00:08:13 +0000