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* Flashrom torture test scriptDavid Hendricks2010-10-292-1/+282
| | | | | | | | | | | Focus is on partial write and layout functionality. Minor modifications by Carl-Daniel Hailfinger. Corresponding to flashrom svn r1218. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix internal offset calculations for SPI BYTE PROGRAM and SPI AAI PROGRAMCarl-Daniel Hailfinger2010-10-272-9/+18
| | | | | | | | | | | | | | | | The bug was invisible so far because we always started at offset 0. The pending partial write patch uses nonzero start offsets and trips over this bug. Clarify a few comments in IT87 SPI. Thanks to Idwer Vollering for reporting write breakage with my latest partial write patch. This should fix the underlying problem. Corresponding to flashrom svn r1217. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Add a reset to probe_jedec before we read the chip's IDsSean Nelson2010-10-202-1/+22
| | | | | | | | | | | | | | | | | | Previous probes might have had too short delays for entering ID mode, so the chip may still be in the process of entering the ID mode. Due to that, an additional delay before the reset makes sense. Add FEATURE_RESET_MASK to deal cleanly with those feature bits. Maciej Pijanka tested the patch and it fixes probing for him with some old Atmel chips. Corresponding to flashrom svn r1216. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Anders Juel Jensen <andersjjensen@gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Always read the flash chip before writingCarl-Daniel Hailfinger2010-10-193-17/+71
| | | | | | | | | | | | | | | | | | | | | This will allow flashrom to skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. A followup patch will make this configurable. Corresponding to flashrom svn r1215. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org>
* Fix board name, EP-8NPAI should have been EP-8NPA7IUwe Hermann2010-10-182-4/+3
| | | | | | | | | | | | | Details, lspci/superiotool/flashrom logs: http://www.flashrom.org/pipermail/flashrom/2010-October/005160.html Also add the vendor website URL for this board. Corresponding to flashrom svn r1214. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add a board enable for the EPoX EP-8NPA7I boardJonathan Kollasch2010-10-152-0/+11
| | | | | | | | | Also, spelling correction. Corresponding to flashrom svn r1213. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Refactor doit()Carl-Daniel Hailfinger2010-10-151-81/+100
| | | | | | | | | | | | | | Doit() is the monster function we split off from main() when we created cli_classic() and tried to introduce some abstraction. doit() is a poster child of WTFs on an astronomic scale. Make doit() less bad by factoring out self-contained code. Corresponding to flashrom svn r1212. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Switch all flash chips to partial writeCarl-Daniel Hailfinger2010-10-1310-100/+61
| | | | | | | | | | | | | | | The inner write functions which handle partial write are renamed to the original name of their wrappers. The write wrappers are removed. Corresponding to flashrom svn r1211. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Andrew Morgan <ziltro@ziltro.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Refactor remaining write wrappersCarl-Daniel Hailfinger2010-10-137-69/+90
| | | | | | | | | | | | | | | | | | | Kill duplicated code. Annotate write functions with their chunk size. Mark Fujitsu MBM29F400BC and ST M29F400BB as untested because their write code no longer uses a broken layout. Corresponding to flashrom svn r1210. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Simplify calls to inner write functionsCarl-Daniel Hailfinger2010-10-106-53/+5
| | | | | | | | | No behavioural changes, just equivalence transformations. Corresponding to flashrom svn r1209. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Unify chip write functionsCarl-Daniel Hailfinger2010-10-109-61/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The currently used write functions (wrappers) all use helpers which perform the actual write (inner functions). The signature of the write wrappers is: int write_chip(struct flashchip *flash, uint8_t * buf); The signature of the inner write functions varied a lot. This patch changes them to: int write_part(struct flashchip *flash, uint8_t *src, int start, int len); Did you know that flashrom has only 8 inner write functions for all flash chips? write_page_write_jedec_common write_sector_jedec_common write_sector_28sf040 spi_chip_write_256_new spi_chip_write_1_new spi_aai_write_new write_page_82802ab write_page_m29f400bt Export all inner write functions. Change the function signature of wait_82802ab to eliminate single-use variables. Remove an error message in write_page_m29f400bt which was printed for every byte written regardless of success. Add sharplhf00l04.c to the list of flash chip drivers in the Makefile. While the functions in there are unused, I suspect we will need them later, and by hooking the file up we ensure that compilation won't break. Corresponding to flashrom svn r1208. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Remove progress printing from individual flash chip driversCarl-Daniel Hailfinger2010-10-087-70/+0
| | | | | | | | | | Progress printing should be handled in the generic code, and will end up there once partial write is possible. Corresponding to flashrom svn r1207. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Move implicit erase out of chip driversCarl-Daniel Hailfinger2010-10-0812-183/+97
| | | | | | | | | | | | | | | | | | Flashrom had an implicit erase-on-write for most flash chip and programmer drivers, but it was not entirely consistent. Some drivers had their own hand-rolled partial update functionality which made handling partial updates from generic code impossible. Move implicit erase out of chip drivers, and kill some dead erase functions at the same time. A full chip erase is now performed in the generic code for all flash chips on write, and after that the whole chip is written. Corresponding to flashrom svn r1206. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Increase flashrom release number to 0.9.3v0.9.3Carl-Daniel Hailfinger2010-10-081-1/+1
| | | | | | | Corresponding to flashrom svn r1204. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Multiple unrelated changesCarl-Daniel Hailfinger2010-10-086-24/+41
| | | | | | | | | | | | | | | CONFIG_BITBANG_SPI was not selected if CONFIG_NICINTEL_SPI was on by default. Wiki output was missing all flash chips if CONFIG_INTERNAL was not selected. Use correct type for toupper()/tolower()/isspace() functions. Specify software requirements in a generic way. Non-x86 compilation does not work with the default programmer set, so list the make parameters which result in a working build. Corresponding to flashrom svn r1203. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Refine text of requests to send logsPaul Menzel2010-10-084-11/+22
| | | | | | | | | | | A lot of messages sent@flashrom.org just have "flashrom -V" as the subject. Ask people to include more information in the subject line to make life easier for developers/supporters. Corresponding to flashrom svn r1202. Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Fix timing of SPI status register writes (WRSR)Carl-Daniel Hailfinger2010-10-082-4/+39
| | | | | | | | | | | SPI write status register (WRSR) may take longer than 100 ms, and it makes sense to poll for completion in 10 ms steps until 5 s are over. This patch complements r1115. Corresponding to flashrom svn r1201. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joshua Roys <roysjosh@gmail.com>
* List the devices for all supported programmers in "flashrom -L" outputCarl-Daniel Hailfinger2010-10-073-30/+40
| | | | | | | | | | | Fix PCI device ID printing. Remove personal e-mail addresses from the man page, point people to flashrom@flashrom.org instead. Corresponding to flashrom svn r1200. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Refine -L output to include all programmer modulesCarl-Daniel Hailfinger2010-10-067-55/+111
| | | | | | | | | | | Flashrom -L output did not contain a list of programmers nor were all programmers listed. Fix it and mention at least the name of each programmer. Wiki output is unchanged, and will need separate fixups. Corresponding to flashrom svn r1199. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Rename Direct I/O library to DirectHWCarl-Daniel Hailfinger2010-10-064-3/+5
| | | | | | | | | | | | | The Direct I/O library for Mac OS X is now called DirectHW to make sure people can find it via an internet search. DirectIO was a generic name for a concept and thus not a good distinguisher for a library. Corresponding to flashrom svn r1198. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com>
* Update the author list in the man pageCarl-Daniel Hailfinger2010-10-062-4/+34
| | | | | | | | | Update programmer parameter documentation. Corresponding to flashrom svn r1197. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Remove duplicate includes from the codeStefan Reinauer2010-10-0616-19/+0
| | | | | | | Corresponding to flashrom svn r1196. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* DJGPP: Avoid leaking memory on lowmem mapping errorCarl-Daniel Hailfinger2010-10-051-1/+5
| | | | | | | | | Add a clarifying comment about why low memory is never unmapped. Corresponding to flashrom svn r1195. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Rudolf Marek <r.marek@assembler.cz>
* Massive speedups for SST25VF032B and SST25VF064CHelge Wagner2010-10-053-5/+20
| | | | | | | | | | | | | Use AAI write for SST SST25VF032B. Speedup from 228 to 113 seconds. Use page (256 byte) write for SST SST25VF064C. Speedup from 3091 to 123 seconds. Corresponding to flashrom svn r1194. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Implement on-the-fly reprogramming of the ICH SPI OPCODE tableHelge Wagner2010-10-051-20/+79
| | | | | | | Corresponding to flashrom svn r1193. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741Uwe Hermann2010-10-053-0/+4
| | | | | | | | | | | | | | This also adds (and marks as tested) a chipset-enable for the SiS 741. All operations successfully tested on hardware. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html Corresponding to flashrom svn r1192. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add board enable for Dell OptiPlex GX1 and mark Intel 28F002BC/BL/BV/BX-T as ↵Mattias Mattsson2010-10-053-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | tested Match on ethernet and north bridge. This is tested on an OptiPlex GX1 400L+ but will probably work for the whole GX1 series as they all share the same vendor BIOS. lspci/flashrom output http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html lspci output (OptiPlex GX1 unknown model) http://www.coreboot.org/pipermail/coreboot/2010-May/058040.html superiotool output (OptiPlex GX1 266L+) http://www.flashrom.org/pipermail/flashrom/2009-July/000207.html lspci/dmidecode output (OptiPlex GX1 266L+) http://www.coreboot.org/pipermail/coreboot/2009-July/050958.html Corresponding to flashrom svn r1191. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Quick fix for broken writes on FT2232H based programmersUwe Hermann2010-10-051-1/+1
| | | | | | | | | | | | | Not sure if this is the final/correct fix, but for now it definately fixes writes on FT2232H hardware. I have tested this on both, the DLP Design DLP-USB1232H, and the openbiosprog-spi hardware. Thanks to Joshua Roys <roysjosh@gmail.com> for the hint on IRC. Corresponding to flashrom svn r1190. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Make sure all chip variants are present in .name strings in flashchips.cMattias Mattsson2010-10-052-30/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by ID. Rename the following constants to their "canonical" name: P28F400BT (0x70 -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Add chip IDs for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Corresponding to flashrom svn r1189. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Speed up RayeR SPIPGM driver by a factor of 2Carl-Daniel Hailfinger2010-10-052-35/+69
| | | | | | | | | | | | | | | Allow specification of an alternate base address with flashrom -p rayer_spi:iobase=0x278 Any base address is allowed as long as it is nonzero, below 65536 and a multiple of four. Read speed is now on par with original spipgm.exe. Corresponding to flashrom svn r1188. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* Board enable for GA-6IEMMichael Karcher2010-10-052-0/+3
| | | | | | | | | | | | | | Reported by Konstantin <hc@comp.susu.ac.ru> lspci (superiotool missing, doesn't matter for this patch) http://www.coreboot.org/pipermail/flashrom/2010-September/004609.html DMI is needed, as there are no usefull PCI IDs. (no test of that board yet, thus marked as untested) Corresponding to flashrom svn r1187. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add details how to build for DOS to READMEIdwer Vollering2010-10-051-3/+4
| | | | | | | | | | Update README to list all the needed rpm files for DOS cross-compilation and update the download location of cwsdpmi. Corresponding to flashrom svn r1186. Signed-off-by: Idwer Vollering <vidwer+flashrom@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add Intel 82571EB and 82572EI Gigabit NICs to the supported listIdwer Vollering2010-10-051-0/+2
| | | | | | | | Corresponding to flashrom svn r1185. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Iain Paton <selsinork@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for building flashrom against libpayloadPatrick Georgi2010-09-306-5/+74
| | | | | | | | | | | This doesn't include changes to the frontend which must be done separately, so this won't work out of the box. This code was tested on hardware. Corresponding to flashrom svn r1184. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Support for Loongson-2F (MIPS) flashingVladimir 'phcoder' Serbinenko2010-09-292-1/+52
| | | | | | | Corresponding to flashrom svn r1183. Signed-off-by: Vladimir 'phcoder' Serbinenko <phcoder@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add list with DMI chassis typesCarl-Daniel Hailfinger2010-09-261-4/+29
| | | | | | | | | | | | | Half a dozen hardcoded strcmp() don't make sense if we need a chassis-type list anyway once we merge the internal DMI decoder. Provide and array of the most interesting chassis types and annotate them with laptop/non-laptop status. Match the dmidecode chassis type against the strings in the array. Corresponding to flashrom svn r1182. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com>
* Implement libpayload support and improve life for DOS based flashrom, tooPatrick Georgi2010-09-253-11/+18
| | | | | | | | | | | | | | Corresponding to flashrom svn r1181. Change the physmap* behaviour to use (void*)-1 as error code instead of NULL. That way, 1:1 mapped memory can be supported properly because (void*)0 is not a magic pointer anymore. (void*)-1 on the other hand is a rather unlikely memory offset, so that should be safe. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* internal: remove unused variablePeter Lemenkov2010-09-201-0/+2
| | | | | | | | | | | | | | | | | The variable 'ret' is unused when compiling on big-endian architecture. This produces an "unused variable" message, which might be treated as error if -Werror was passed to compiler. With this patch I was able to compile flashrom cleanly on ppc and ppc64: http://koji.fedoraproject.org/koji/taskinfo?taskID=2472482 http://koji.fedoraproject.org/koji/taskinfo?taskID=2472484 Corresponding to flashrom svn r1180. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add chip IDs for Alliance Semiconductor flash chipsMattias Mattsson2010-09-181-0/+12
| | | | | | | | | | | | | | | | | | | Cross-checked with UniFlash 1.40 source, chip datasheets and EZoFlash's chip database (http://www.ezoflash.com/chip_database.php). Datasheets: http://www.ezoflash.com/datasheets/flash/Alliance/AS29F002.pdf http://www.alsc.com/pdf/flash.pdf/as29f010.pdf http://www.alsc.com/pdf/flash.pdf/as29f040.pdf http://www.alsc.com/pdf/flash.pdf/as29f200.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV160.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV400.pdf http://www.ezoflash.com/datasheets/flash/Alliance/AS29LV800.pdf Corresponding to flashrom svn r1179. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Handle Bus Pirates already in bit banging mode correctlyCarl-Daniel Hailfinger2010-09-162-2/+27
| | | | | | | | | | | | | | | | | | | | Thanks to Johannes Sjölund for reporting that the Bus Pirate init could not deal with a Bus Pirate which is already in binary Bitbang mode. This is caused by a combination of the slowness of the Bus Pirate, the slowness of USB and a fast serial port flush routine which just flushes the buffer contents and does not wait until data arrival stops. Make the Bus Pirate init more robust by running the flush command 10 times with 1.5 ms delay in between. This code development was sponsored by Mattias Mattsson. Thanks! Tested a few dozen times, should work reliably. Corresponding to flashrom svn r1178. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mattias Mattsson <vitplister@gmail.com>
* Add board enable for Elitegroup GeForce6100SM-MMattias Mattsson2010-09-162-0/+25
| | | | | | | | | | | | | | | | Match on Memory Controller/LPC Bridge. lspci/superiotool output: http://www.coreboot.org/pipermail/flashrom/2010-September/004829.html Test report: http://www.coreboot.org/pipermail/flashrom/2010-September/004835.html Corresponding to flashrom svn r1177. Tested-by: Andrew Cleveland <evil.saltine@gmail.com> Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add chip definitions for the folowing chipsJoshua Roys2010-09-162-0/+84
| | | | | | | | | | | | | | | | | | | | | | | Bright BM29F040 Hyundai HY29F040A Macronix MX29F040 Also add chip IDs for Bright BM29F400T/B Datasheets: http://www.ezoflash.com/datasheets/flash/Winbond/BM29F040.pdf http://www.ezoflash.com/datasheets/flash/Hyundai/HY29F040A.pdf http://www.ezoflash.com/datasheets/flash/Macronix/MX29F040.pdf http://www.ezoflash.com/datasheets/flash/Winbond/BM29F400T_B.pdf Bright BM29F040 probe/read test report: http://www.flashrom.org/pipermail/flashrom/2010-September/004805.html Corresponding to flashrom svn r1176. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Mattias Mattsson <vitplister@gmail.com>
* This patch changes the prefix of chip constant #defines in the following wayMattias Mattsson2010-09-153-456/+456
| | | | | | | | | | | | | | | | | | | | | | | | AM_* -> AMD_AM* AT_* -> ATMEL_AT* EN_* -> EON_EN* HY_* -> HYUNDAI_HY* MBM* -> FUJITSU_MBM* MX_ID -> MACRONIX_ID MX_* -> MACRONIX_MX* PMC_* -> PMC_PM* SST_* -> SST_SST* It leaves the Intel #defines alone because there is another pending patch for that: http://patchwork.coreboot.org/patch/1937/ Some background discussion here: http://www.flashrom.org/pipermail/flashrom/2010-July/004059.html Corresponding to flashrom svn r1175. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add chipset enable for Broadcom OSB4Joshua Roys2010-09-151-0/+18
| | | | | | | | | No docs available. Corresponding to flashrom svn r1174. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Detect embedded EC (IMC) in AMD's SBsCarl-Daniel Hailfinger2010-09-151-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | AMD SB700 and later have an integrated microcontroller (IMC) which runs from shared flash. The IMC will happily issue reads while we write, issue writes while we read, and generally cause lots of havoc due to the concurrent accesses it performs while flashrom is running. A failing or corrupted read can be detected since r1145, and the worst case is that the read aborts and the user has to retry. A failing write is much more serious. It can be detected since r1145, but if the SPI interface locks up, we can't continue writing nor can we read the current chip contents. If the IMC is inactive, there is no reason to worry. If the IMC is active, flashrom will refuse to erase/write the chip with this patch. The correct fix would be to stop the IMC during flashing, but apparently the relevant registers are undocumented, so we take the safe route for now until someone from AMD can give us more info. Corresponding to flashrom svn r1173. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Matthias Kretz <kretz@kde.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Delay between probe and subsequent operationsCarl-Daniel Hailfinger2010-09-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Some flash chips need time to exit ID mode, and while we take care of correct timing for the matching probe, subsequent probes may have totally different timing, and that can lead to garbage responses from the flash chip during the first accesses after the probe sequence is done. Delay 100 ms between the last probe and any subsequent operation. To ensure maximum correctness, we would have to reset the chip first in case the last probe function left the chip in an undefined (non-read) state. That will be possible once struct flashchip has a .reset function. This fixes unstable erase/read/write for some flahs chips on nic3com and possible other use cases as well. Thanks to Maciej Pijanka for reporting the issue and testing patches. Corresponding to flashrom svn r1172. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
* SPI bitbanging: request/release busCarl-Daniel Hailfinger2010-09-154-21/+53
| | | | | | | | | | | | | | | | | | | | | | | | | SPI bitbanging on devices which speak SPI natively has a dual-use problem: We need to shut down normal SPI operations to do the bitbanging ourselves. Once we're done, it makes a lot of sense to reenable "normal" SPI operations again. Add request_bus/release_bus functions to struct bitbang_spi_master. Add a bitbang shutdown function (not used yet). Change MCP SPI and Intel NIC SPI to use the new request/release bus infrastructure. Cosmetic changes to a few error messages (80 column limit). There are multiple possible strategies for bus request/release: - Request at the start of a SPI command, release immediately afterwards. - Request at the start of a SPI multicommand, release once all commands of the multicommand are done. - Request on programmer init, release on shutdown. Each strategy has its own advantages. For now, we will stay with the first strategy which worked fine so far. Corresponding to flashrom svn r1171. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Honor ICH SPI address window for readsCarl-Daniel Hailfinger2010-09-151-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | ICH SPI has the ability to restrict SPI read/write accesses to a given address range. The low end of the range is configurable by the BIOS (and by flashrom if the BIOS didn't lock down the flash interface), the high end of the range is 0xffffff (2^24-1). This patch checks for an address range restriction and uses the low end of the allowed range as base for SPI reads. A similar workaround for REMS/RES opcodes has been committed in r500. This fixes read on the Intel D945GCLF mainboard where the stock BIOS enforces a restricted address range. Please note that writes need the same fix, but for architectural reasons that fix will be merged once partial write is available. Corresponding to flashrom svn r1170. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested by David Hendricks on the Intel D945GCLF mainboard, results at http://paste.flashrom.org/view.php?id=79 Acked-by: David Hendricks <dhendrix@google.com>
* Add missing GIGABYTE GA-7DXR entry, should have been in r1166Uwe Hermann2010-09-151-0/+1
| | | | | | | Corresponding to flashrom svn r1169. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Various style/consistency fixes mainly for Winbond chipsMattias Mattsson2010-09-142-97/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename constants W_nnnn -> WINBOND_Wnnnn W_25nnn -> WINBOND_NEX_W25nnn. Kill incorrect ASD chip and vendor id. Group Winbond SPI and parallel chips separately (they have different vendor IDs). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> WINBOND_W29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> WINBOND_W29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> WINBOND_W29C010 (Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008) List all chip variants in the .name strings in flashchips.c Have two identical entries for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 but with different probe functions in flashchips.c as sometimes (for newer revisions of these chips?) the standard jedec probe seems to work. E.g. see test report here: http://patchwork.coreboot.org/patch/1476/ Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Corresponding to flashrom svn r1168. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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