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* util/lint: Introduce linter for git sign-off-by lineFelix Singer2022-12-063-0/+75
| | | | | | | | | | | | | | | | | | | | | For compliance and to check if the commit message matches the development guidelines, add a linter checking for the sign-off-by line in the commit message. Also, hook it up to the test_build.sh script which is used for CI builds. These scripts were copied from the coreboot repository and were adjusted so that they work for flashrom. Original-Signed-off-by: Felix Singer <felixsinger@posteo.net> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70079 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Add 4BA write to XM25Qx256CLiam Flaherty2022-12-061-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Flash chips XM25QH256C and XM25QU256C support the 4-byte program command (0x12) according to their datasheets, but the feature flag is not enabled in flashchips.c, so enable it to allow this feature to be used. TICKET: https://ticket.coreboot.org/issues/371 BUG=b:259493706 TEST=build Original-Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713 Original-Reviewed-by: Felix Singer <felixsinger@posteo.net> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libpayload: Fix compiling bugsThomas Heijligen2022-12-012-1/+3
| | | | | | | | | | | | | | | | | | | | hwaccess_physmap.c: make `void *sys_physmap()` static hwaccess_x86_io.c: Add missing include Original-Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69831 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Felix Singer <felixsinger@posteo.net> Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Fix number of bytes for HW seq operationsSubrata Banik2022-12-011-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Original-Signed-off-by: Subrata Banik <subratabanik@google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70039 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Clear Fast SPI HSFC register before HW seq operationSubrata Banik2022-12-011-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a regression introduced with commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out common hwseq_xfer logic into helpers). The reason for the regression is ignoring the fact that the Fast SPI controller MMIO register HSFC (0x06) might not hold the default zero value before initiating the HW sequencing operation. Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent a byte that needs to be transfered. While debugging the regression, we have observed that the default value in the FDBC (prior to initiate any operation) is 0x3f (instead of zero) which represents 64-byte transfer. localhost ~ # iotools mmio_read32 0x92d16006 0x3f00 <Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06> FDBC offset during `--wp-disable` operation represents higher numbers of bytes than the actual and eventually results in the error. Additionally, dropped unused variable (struct hwseq_data *hwseq_data). BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. Without this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x3f11 With this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x0 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x11 Additionally, verified other HW sequencing operations (like read, write, erase, read status, write status, read ID) working fine without any error. Original-Signed-off-by: Subrata Banik <subratabanik@google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69998 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* opaque_master: Mark Opaque chip as tested for WPAnastasia Klimchuk2022-12-013-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opaque masters, by design, populate the flashchip structure during the execution of their probe function. Therefore any opaque master operation displays a message to the user: "This flash part has status UNTESTED for operations: WP". However, for all the other operations (read, write, erase) opaque masters always mark them as tested. Thus, align WP as marked tested inline with other opaque chip operations. BUG=b:258755442 TEST=the following does not display untested message: 1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE 2) flashrom -p internal (on Intel device) Original-Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Original-Reviewed-by: Felix Singer <felixsinger@posteo.net> Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* linux_mtd: Mark Opaque chip as tested for WPAnastasia Klimchuk2022-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since linux_mtd supports write-protect, its probe function needs to mark Opaque chip as tested for WP. Programmers which are opaque masters are responsible for populating flashchip#tested struct in probe function. Without the patch, any operation running via linux_mtd displays a message "This flash part has status UNTESTED for operations: WP". With the patch, the message is not displayed anymore. BUG=b:258755442 BRANCH=none TEST=flashrom -p host on ARM dut Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) on host. No operations were specified. Original-Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* cli_classic.c: Be consistent with pointer typesAngel Pons2022-12-011-2/+2
| | | | | | | | | | | | | | | | | | | | | With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as `long unsigned int`, which is not the same as `unsigned int`. As the `flashrom_layout_get_region_range()` function is part of libflashrom API, adjust `cli_classic.c` instead to avoid type mismatches. Original-Signed-off-by: Angel Pons <th3fanbus@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451 Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-by: Evan Benn <evanbenn@google.com> Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Revert "libflashrom: Return progress state to the library user"Edward O'Callaghan2022-11-1022-184/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 40892b0c08fbc8029921e91511dd3f91fc956f90. The feature of returning progress for libflashrom users was introduced in original commit, however later a bug was found and reported as https://ticket.coreboot.org/issues/390. Reverting in a release branch to unblock release candidate, since it is unknown how much time needed to fix the bug. Meanwhile the feature remains in a master branch and will be fixed under ticket 390. TEST=scenarios below run successfully 1) flashrom -h does not show --progress 2) flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin 3) flashrom -p dummy:emulate=W25Q128FV -v /tmp/dump.bin 4) flashrom -p dummy:emulate=W25Q128FV -E 5) head -c 16777216 </dev/urandom >/tmp/image.bin flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV \ -w /tmp/dump.bin Change-Id: Id3d7ffcaf266a60a44eb453fd09b7c63c05349c2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* sb600spi.c: Drop "Promontory" supportAngel Pons2022-11-061-42/+0
| | | | | | | | | | | | | | | | The "Promontory" code is riddled with issues, some of them can result in soft bricks. Moreover, Promontory doesn't have a SPI controller. Drop support for "Promontory" in flashrom for now: it's holding back the entire project and it's unlikely that it'll be fixed in a timely manner. Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi.c: heap allocate hwseq_data to remove globalEdward O'Callaghan2022-11-031-6/+18
| | | | | | | | | | | | Align hwseq path in ichspi with the rest of the flashrom tree by making hwseq_data a heap allocation within the life-time of the driver managed by the driver registration API. Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer()Edward O'Callaghan2022-11-031-1/+2
| | | | | | | | | | | | | Allow helpers to derive driver specific data from the driver specific context instead of being a closure over a static global variable. Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ichspi.c: plumb flashctx through hwseq xfer helperEdward O'Callaghan2022-11-031-8/+9
| | | | | | | | | | | | Change is a NOP to prepare ichspi to remove hwseq_data being a global symbol in CB:68774. This allows for the helper functions to derive their data from the driver data context. Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tests/meson.build: Rename list of source files to `test_srcs`1.3.x_infdevFelix Singer2022-11-011-3/+3
| | | | | | | | | | | | Rename the list of source files to `test_srcs` so that there is less confusion with the variable `srcs` from the top-level meson.build file containing the flashrom source files. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ica0fc3923070bff63323204bd58edb5276dc9493 Reviewed-on: https://review.coreboot.org/c/flashrom/+/68228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree/: Convert flashchip read func ptr to enumerateEdward O'Callaghan2022-11-017-607/+654
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I612d46fefedf2b69e7e2064aa857fa0756efb4e7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66788 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip write func ptr to enumerateEdward O'Callaghan2022-11-017-599/+656
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I80149de169464b204fb09f1424a86fc645b740fd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip probe func ptr to enumerateEdward O'Callaghan2022-11-014-596/+650
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I00aaab9c83f305cd47e78c36d9c2867f2b73c396 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* writeprotect: Add some debug logging if wp_verify failsEvan Benn2022-10-311-3/+8
| | | | | | | | | | Change-Id: I5fcaf767570418f90ae44826a1135d9b49653033 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67720 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Mark Intel C246 as DEPAngel Pons2022-10-311-1/+1
| | | | | | | | | | | | Tested reading, writing and erasing the flash chip of a Prodrive Hermes mainboard with an Intel C246 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I07d6c4a60e468c61eba836db91e1335f4a762048 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* nicintel_eeprom.c: Fix typoFelix Singer2022-10-311-4/+4
| | | | | | | | | | | `done_i20_write` is meant to be `done_i210_write`. Fix that. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Idc0a0c475e891fc8538a7a81093520e01e1b25bf Reviewed-on: https://review.coreboot.org/c/flashrom/+/68582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* MAINTAINERS: Add Felix Singer for test_build.shFelix Singer2022-10-311-0/+5
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I36267e6c080b14e90e820d3e26abaefe642f9c65 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom.c: Move count_max_decode_exceeding() to cliEdward O'Callaghan2022-10-313-44/+43
| | | | | | | | | | | | The count_max_decode_exceeding() function is only ever called within the cli_classic logic so move it there and make it static. This further cleans up the flashrom.c symbol namespace. Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip decode range func ptr to enumNikolai Artemiev2022-10-284-28/+51
| | | | | | | | | | | | | | | | | | | | Replace the `decode_range` function pointer in `struct flashchip` to an enum value. The enum value can be used to find the corresponding function pointer by passing it to `lookup_decode_range_func_ptr()`. Removing function pointers like `decode_range` makes it possible to represent chip data in a declarative format that does not have to be stored as C source code. BUG=b:242479049 BRANCH=none TEST=ninja && ninja test Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6d08d414d3d1ddadc95ca1d407fc87c23ab543d Reviewed-on: https://review.coreboot.org/c/flashrom/+/67195 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark WP of 9 entries as testedSergii Dmytruk2022-10-231-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on information from: * commit a850fd0aa8054a1125a9231fa3317428f15900f4 - GD25LQ128C/GD25LQ128D/GD25LQ128E - GD25LQ64(B) - GD25Q127C/GD25Q128C - GD25Q256D/GD25Q256E - GD25Q64(B) * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba - GD25Q32(B) * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8 - W25Q64BV/W25Q64CV/W25Q64FV * https://github.com/Dasharo/dasharo-issues/issues/67 - W25Q128.V..M * https://github.com/Dasharo/flashrom/pull/8 - W25Q64.W Change-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Kamil Pokornicki <kamil.pokornicki@3mdeb.com> Tested-by: Przemyslaw Banasiak <przemyslaw.banasiak@3mdeb.com> Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flash.h: extend `struct tested` with .wp fieldSergii Dmytruk2022-10-233-12/+23
| | | | | | | | | | | | Using "B" letter for "block protection" in TEST_* macros. Ticket: https://ticket.coreboot.org/issues/377 Change-Id: I791400889159bc6f305fb05f3e2dd9a90dbe18a4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68179 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* rayer_spi.c: Get rid of temporary `prog_type` stringAngel Pons2022-10-221-14/+8
| | | | | | | | | | | | | Make the `get_params()` function provide a pointer to `struct rayer_programmer` directly, instead of having a `prog_type` string passed around three functions. Change-Id: I83e34382ee9814f224025e21e5099fdab73cee8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68239 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* rayer_spi.c: Roll up programmer type search logic into funcEdward O'Callaghan2022-10-221-24/+33
| | | | | | | | | | | | Roll up the programmer type table search and match logic into it's own function and lexically scope the 'rayer_spi_types' table into the function while we are here. Change-Id: Id226ea61132ecc30fd8696e1d8ea50373e752cac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* rayer_spi.c: Drop lpt_outbyte intermediate varEdward O'Callaghan2022-10-221-5/+2
| | | | | | | | | | | | | The intermediate variable in this case serves no extra assistance in readability or additional control flow branching. Just assign the result directly into the driver state tracker. Change-Id: Idedabb7b1c401d666b3b7e621e75704c7e765fd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* rayer_spi.c: Move param parse logic into own funcEdward O'Callaghan2022-10-221-21/+36
| | | | | | | | | | | Deconvolve programmer parameter parse logic out of main 'rayer_spi_init()' entry-point function control flow. Change-Id: I287aa2e5d94e872553d08c0750f8dc6d60b9caff Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: Remove fixme with explanationLiam Flaherty2022-10-211-1/+5
| | | | | | | | | | | | | | | | | | The raiden_debug_spi programmer will query the connected USB devices and match against criteria other than the pid rather than iterate through the vid:pid table. The fixme has been updated to explain why the dev_entry table is empty. TICKET: https://ticket.coreboot.org/issues/394 BUG=b:253320285 TEST=build Change-Id: I43e364c02f42dd499d3c9ca3e0a03ead673da3e6 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: provide flashrom context into programmer_delay()Alexander Goncharov2022-10-1726-96/+97
| | | | | | | | | | | | | | | | | Modify the `programmer_delay` function signature to allow passing the flashrom context. Programmers that depend on internal delay should provide NULL as a context. The use of this function parameter will be introduced in CB:67393. TOPIC=programmer_handle_global TEST=builds Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.c: Use programmer_init() func params over globalEdward O'Callaghan2022-10-161-2/+2
| | | | | | | | | | | | The 'programmer' intended to be used in the control flow of 'programmer_init()' is a parameter to the function. Therefore use that symbol directly over the global copy of it. Change-Id: I71e61f0633bac2fc472971249910bf3bf57cd0eb Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dirtyjtag: Add DirtyJTAG programmerJean THOMAS2022-10-158-5/+363
| | | | | | | | | | | | | | | | Add a new programmer driver for the DirtyJTAG project (a USB-JTAG firmware for STM32 MCUs). Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103 development board and a SST25VF020B SPI flash chip. Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913 Signed-off-by: Jean THOMAS <virgule@jeanthomas.me> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashrom.c: Separate out default layout initEdward O'Callaghan2022-10-151-6/+13
| | | | | | | | | | | | | get_default_layout() is undefined without a init_default_layout() so separate out that logic from probe_flash(). Change-Id: I8fd0af8fb1c32dc9f2b00cc39b518d2f4d98e3ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* layout.c: Use calloc() to ensure a zeroed layoutEdward O'Callaghan2022-10-151-3/+1
| | | | | | | | | | | | No need to malloc() and then do a DIY memset to zero of the heap. Just use calloc(1, ..) to get a zeroed heap. Change-Id: Id6cf2c4591aec0620f15d8a39495d2bff6597f96 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tests/meson.build: Turn file list into list of file objectsFelix Singer2022-10-151-2/+2
| | | | | | | | | | | | | | | | | When a file object is created, Meson also checks if the file actually exists and an error points to the specific line of meson.build if not. If just a list of filenames is used, then the error occurs at the line where the list is used. Thus, use file objects in tests/meson.build for more useful error messages. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I0b9144a6b76c1772833817b4e6873818dcf36b05 Reviewed-on: https://review.coreboot.org/c/flashrom/+/68197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.8.tmpl: document mediatek_i2c_spi programmerPeter Marheine2022-10-111-1/+24
| | | | | | | | | | | | | This adds a manpage section describing the mediatek_i2c_spi programmer, including some discussion of devices that are supported as well as which systems use them. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: Ia63df470170fbadcabadcdad8e5acc0cde3a274b Reviewed-on: https://review.coreboot.org/c/flashrom/+/67825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* meson.build: Fix indentation of mstarddc_spi definitionFelix Singer2022-10-111-1/+1
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I064b50f87760fd7ad40b3629b3fa68552c8ddb46 Reviewed-on: https://review.coreboot.org/c/flashrom/+/68163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.c: create is_internal_programmer() helperEdward O'Callaghan2022-10-101-7/+12
| | | | | | | | | | | | | | | | | | As suggested by Angel Pons, add the function `is_internal_programmer` to cut down on some pre-processor usage by moving it into the new function. The function then checks if the internal programmer is the selected one. If the internal programmer is not built in, then it just returns false. Change-Id: I43243b990192077583a9a3a95d35844923d9c158 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* manibuilder/apt-get: Drop `apt-get dist-upgrade` commandsNico Huber2022-10-083-3/+0
| | | | | | | | | | Such invasive updates shouldn't be needed. And if, we'd notice. Change-Id: I8915ad0f8b348c1bb532c261a73ea2ab6d602565 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* s25f.c: Fix undefined behaviour on shiftEvan Benn2022-10-081-4/+4
| | | | | | | | | | | | | | | | | dev_id, a uint8_t, was shifted left by 24 bits. After promotion to int, this results in shifting into the sign bit, which is undefined behaviour. Cast to uint32_t to prevent the promotion to signed int. BUG=None BRANCH=None TEST=None Change-Id: I88188ef2ba2af919eeae9ba08916374d31d8b989 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.c: Remove custom mappers from opaque_masterJonathon Hall2022-10-082-11/+3
| | | | | | | | | | | | | No opaque masters have a custom mapper. The returned chipaddr is not fed back into the read/write/erase functions, so this would only be useful for side effects. Change-Id: I36f05154edda371b51f8ff416f019837ff1c243d Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68092 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher.c: Remove custom mapper from opaque_masterJonathon Hall2022-10-081-2/+0
| | | | | | | | | | | | | | | | Dummy doesn't need a custom mapper on opaque_master; the returned address is not used and the mapper has no side effects. This is the only remaining opaque master with a custom mapper, so this permits removing custom mapper support from opaque masters. Change-Id: I76ae3e0c2e91ecba4fd320941bd1eff038050731 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68091 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi: Do not attempt to map physical memory for hwseqJonathon Hall2022-10-081-2/+0
| | | | | | | | | | | | | | | | ICH hwseq does not need to actually mmap flash, and this fails for flash chips >16 MB, since only the top 16 MB is mapped into the address space. Test: Read and write flash on ICH hwseq with 32 MB flash chip. Change-Id: Ie698071c3181e988f10b750b0e50c9700efaa1a3 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68090 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers: Move (un)map_flash_region to par/spi/opaque_masterJonathon Hall2022-10-0813-41/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | Move (un)map_flash_region function pointers from programmer_entry to par_master, spi_master, and opaque_master. This enables programmers to specify a different mapper per bus, which is needed for the internal programmer. Mapping is closely tied to the way the memory is accessed using the other functions in the bus master structs. Validate that FWH/LPC programmers provide specialized mapping in register_par_master(); this is needed for chips with FEATURE_REGISTERMAP, which only exist on FWH or LPC buses. programmer.c: Update comment in fallback_map(), NULL return is the desired behavior. Test: Read firmware on SB600 Promontory mainboard (requires physmap) Test: Read firmware externally with ft2232_spi Test: Read firmware on ICH hwseq, verify physmap still occurs Change-Id: I9c3df6ae260bcdb246dfb0cd8e043919609b014b Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Co-Authored-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/: Make 'fallback_{un}map' the default unless definedEdward O'Callaghan2022-10-0837-80/+9
| | | | | | | | | | | | | | | | | | | Drop the explicit need to specify the default 'fallback_{un}map' callback function pointer from the 'programmer_entry' struct. This is a reasonable default for every other driver in the tree with only a select few exceptions [atavia, serprog, dummyflasher and internal]. Thus this simplifies driver development and paves way to remove the 'programmer' global handle. Change-Id: I5ea7bd68f7ae2cd4af9902ef07255ab6ce0bfdb3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cli_classic.c: Add error messages for invalid --wp-region useNikolai Artemiev2022-09-301-1/+9
| | | | | | | | | | | | | | Print errors if --wp-region is used without a layout file or the layout file doesn't contain the region. BUG=b:247055486 TEST=builds Change-Id: Ie606ba7f8a423405099679ca62169c395d994b5d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* manibuilder: Maintain list of broken imagesNico Huber2022-09-271-0/+11
| | | | | | | | | | | | | Disable images that can't be built anymore by default. We keep them listed, so existing images can still be used. Also add commands to show and run all supposed-to-be working tags. Change-Id: I0f0ffb6c5e28348656aac2ce265f8b1dc0e93362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* manibuilder/alpine: Disable https for Alpine 3.7 and 3.8Nico Huber2022-09-272-1/+6
| | | | | | | | | | | | | Alpine Linux 3.7 and 3.8 fell behind with their pre-installed cer- tificates. Plus, there seems to be no way to override certificate checks when downloading packages. Hence, disable https completely. Change-Id: I49dc3a2a2d44f948182e7571f6289b74e6fa6eb4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mainbuilder/djgpp: Disable TLS verification for curl and GitNico Huber2022-09-271-2/+3
| | | | | | | | | | | | This image is based on an old unsupported SUSE version. The ca-certificates don't get updates anymore. Change-Id: Ie46e3772f030765d6abb092727e2fbed61d3d989 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 18:41:55 +0000