summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* VERSION: Update version to 1.4.0-rc2v1.4.0-rc2mainAnastasia Klimchuk10 days1-1/+1
| | | | | | | | Change-Id: I725dbbbd43b3b51a5034f5a940ab7a72530bac80 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* libflashrom.map: remove non-existent functionsFabian Groffen2024-07-041-3/+0
| | | | | | | | | | | | Remove symbol names from the map that do not exist in the code. https://bugs.gentoo.org/928955 Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f Signed-off-by: Fabian Groffen <grobian@gentoo.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83261 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* VERSION: Update version to 1.4.0-rc1v1.4.0-rc1Anastasia Klimchuk2024-06-281-1/+1
| | | | | | | | Change-Id: I013a35de898cbd5c09d254baccb3d644c1def2a0 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: Add Support for XMC XM25QH16C/XM25QH16DSsunk2024-06-272-0/+39
| | | | | | | | | | | | | Add initial support for the SPI flash chip XM25QH16C/XM25QH16D Datasheet link: https://www.xmcwh.com/uploads/798/XM25QH16C_Ver1.8.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad Signed-off-by: Kan Sun <ssunkkan@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83182 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add Support for XMC XM25QU80BSsunk2024-06-272-0/+39
| | | | | | | | | | | | | Add initial support for the SPI flash chip XM25QU80B Datasheet link: https://www.xmcwh.com/uploads/520/XM25QU80B_Ver1.4.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5 Signed-off-by: Kan Sun <ssunkkan@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83180 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ich_descriptors_tool: Add Panther Lake SoC to supported chipsetsSubrata Banik2024-06-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change extends the ich_descriptors_tool to recognize and process descriptors for Intel's upcoming Panther Lake SoC. BUG=b:347669091 TEST=ich_descriptors_tool is able to detect "panther" chipset and show below information: > ./util/ich_descriptors_tool/ich_descriptors_tool Need the file name of a descriptor image to read from. usage: './util/ich_descriptors_tool/ich_descriptors_tool -f <image file name> [-c <chipset name>] [-d]' ... ... To also print the data stored in the descriptor straps you have to indicate the chipset series with the '-c' parameter and one of the possible arguments: - "ich8", - "ich9", - "ich10", - "apollo" for Intel's Apollo Lake SoC. - "gemini" for Intel's Gemini Lake SoC. - "jasper" for Intel's Jasper Lake SoC. - "meteor" for Intel's Meteor Lake SoC. - "panther" for Intel's Panther Lake SoC. ... ... - "300" or "cannon" for Intel's 300 series chipsets. - "400" or "comet" for Intel's 400 series chipsets. - "500" or "tiger" for Intel's 500 series chipsets. - "600" or "alder" for Intel's 600 series chipsets. Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83149 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Add support for Panther LakeSubrata Banik2024-06-274-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Panther Lake support into flashrom as per Intel Panther Lake SPI programming doc, number: 815466. BUG=b:347669091 TEST=Flashrom is able to detect PTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Panther Lake-U/H 12Xe". .... > flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Panther Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* hwaccess_x86_io: Fix Android compilation with bionic libcJakub Czapiga2024-06-271-3/+4
| | | | | | | | | | | | | | | | Recently Android Bionic LibC got sys/io.h. Use this header to access ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(), etc. Tested on Android 14 by adding flashrom and pciutils as external repositories, adding Android.bp blueprints (Android specialized build system - Soong), building, running and accessing (read, erase, write) SPI flash on x86 device. Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83133 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Set default wp test status for chips with custom configAnastasia Klimchuk2024-06-251-6/+6
| | | | | | | | | | | | | | | Without this, default value is the first in enum, which is OK. While in reality, for the chips in the patch block-protection is not available, so should be NA. wp test status support was introduced later than the others, so old chips don't have this field initialised. Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83132 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* print.c: Print B (block-protect) test status of the chipsAnastasia Klimchuk2024-06-251-3/+13
| | | | | | | | | | | | | This also expands the column for test status by 1 more char, since now maximum status is longer, PREWB vs PREW. print.c runs when command line option `flashrom -L` is invoked. Change-Id: If697fe3ba93dbe34bb8f7a9a4b1686fdb8b3ee58 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83131 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: add GD25LB256E chip modelVictor Lim2024-06-251-2/+2
| | | | | | | | | | | | | | adding GD25LB256E to the model GD25LR256E which share the same feature. The datasheet link https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00513-GD25LB256E-Rev2.0.pdf Tested read, write, erase, --wp-enable, --wp-disable, --wp-list and --wp-range Change-Id: I0aa520b068a86098f6b4a1b68401c425b33e501f Signed-off-by: Victor Lim <vlim@gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83140 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ich_descriptor: Fix chipset_names index for Intel Meteor LakeSubrata Banik2024-06-241-1/+2
| | | | | | | | | | | | | | | | | | | | | commit hash 85b977151b8f57 (ichspi.c: Add support for region 9 and beyond in Meteor Lake) moved the Intel Meteor Lake macro in programmer.h, causing flashrom to display an incorrect chipset name for Meteor Lake platforms. This patch updates the corresponding chipset_names index to resolve this issue. TEST=Verified correct chipset name in flashrom output for Meteor Lake chipset (google/rex0 board). Change-Id: Ic09cf0474c980369bcbf90924d45f697bc1b0a0d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83143 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc: Add current numbers of supported devices to the intro pageAnastasia Klimchuk2024-06-231-2/+12
| | | | | | | | | | | | | | Current numbers are taken from the output of `flashrom -L` command. Intro page still has a room for improvement, but as a first step the numbers need to be updated. In future, maybe there is a way to update the numbers less manually. Change-Id: I7531521955dcf01348ed2ba9c54316b32b9cd925 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83130 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* print.c: Print total numbers of supported USB and PCI devicesAnastasia Klimchuk2024-06-231-3/+13
| | | | | | | | | | | | | | | | This adds two lines at the very end of the section with supported deviced per programmer. At the moment of this patch, numbers are: Supported USB devices, total 30 Supported PCI devices, total 94 All other sections print total numbers, this was only one missing. Change-Id: Ie011db3985172d05f5160d1cb1cc39a4422a5750 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83129 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Remove Thomas Heijligen from build system and sphinx docsThomas Heijligen2024-06-191-2/+0
| | | | | | | | | Change-Id: I775d2dca95ee6f6d565a24f1622ee70554e9d4f5 Signed-off-by: Thomas Heijligen <src@posteo.de> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* MAINTAINERS: Add Anastasia Klimchuk for CI scriptAnastasia Klimchuk2024-06-161-0/+5
| | | | | | | | Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: Add support for chip model GD25LB128E/GD25LR128EVictor Lim2024-06-161-1/+1
| | | | | | | | | | | | | | | | | Adding GD25LB128E/GD25LR128E to flashchip.c These part # sharing the same ID, form, fit, function, produced with different process node: 1.8V 128Mbit Datasheet Link: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00533-GD25LQ128E-Rev1.1.pdf https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00641-GD25LB128E-Rev1.1.pdf https://www.gigadevice.com/message-board?cid=39&id=3004&file_type=Datasheet&file_name=GD25LR128E Change-Id: I8e8ad6bd69e2159b7cc2b64a7a8c7fcb1399294d Signed-off-by: Victor Lim <vlim@gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* doc: Add doc for supported boards and laptopsAnastasia Klimchuk2024-06-122-0/+20
| | | | | | | | Change-Id: Iaae05ccd138fd8f7760823f867f3c7799018dc2e Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82271 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc: Add doc for supported chipsetsAnastasia Klimchuk2024-06-122-0/+22
| | | | | | | | Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: add support for chip model Winbond W25Q16JV_MMichael Heimpold2024-06-122-0/+53
| | | | | | | | | | | | | | | This is a 2 MiB model with QE=0 factory setting. Tested with ch341a programmer: probe, read, write, erase Link to datasheet: https://www.winbond.com/resource-files/w25q16jv%20spi%20revh%2004082019%20plus.pdf Change-Id: Ida1ceb5fe31411bef647e5133c5bd0bdb02d7704 Signed-off-by: Michael Heimpold <mhei@heimpold.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82715 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* erasure_layout: Fix get_flash_region bugPeter Marheine2024-06-114-92/+599
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When flash regions are protected, erase could incorrectly erase regions which were meant to be protected by requesting the correct size but using an erase opcode with coarser granularity than desired (for instance using a 16-byte erase command while attempting to erase only 8 bytes). This fixes that by exchanging the nesting of the loops over erase blocks and flash regions. Old: - Select erasefns - Loop over blocks to erase for each selected erasefn - Loop over programmer flash regions within erase block - Erase regions (may fail since selected erasefn will be too big if flash region is smaller than erase block) New: - Loop over programmer flash regions within erase block - Select erasefns within programer flash region - Loop over blocks to erase for each selected erasefn - Erase regions Eraser selection and erasing has also been factored out into a helper function to manage nesting depth. TEST=New test cases pass, whereas some of them fail without the changes to erasure_layout.c BUG=https://ticket.coreboot.org/issues/525 Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9 Co-authored-by: Nikolai Artemiev <nartemiev@google.com> Co-authored-by: Anastasia Klimchuk <aklm@flashrom.org> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* doc: Convert ME and Intel docsAnastasia Klimchuk2024-06-064-173/+252
| | | | | | | | | | | | | ME page existed on wiki here https://wiki.flashrom.org/ME The contents are mostly unchanged, but one broken kernel link is removed from Intel doc. Change-Id: I79af5674f3af9ca880e89becd6a272a2cf8ed599 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ch347_spi: Add driver support for CH347F packagingZhiYuanNJ2024-06-021-21/+29
| | | | | | | | | | | | | CH347F can work simultaneously with SPI, I2C and other signals. CH347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Signed-off-by: ZhiYuanNJ Liu <871238103@qq.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
* flashchips: Add support for MXIC MX25R4035FDanielZhang2024-06-022-0/+48
| | | | | | | | | | | | | | | | | The MX25R4035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R4035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8671/MX25R4035F,%20Wide%20Range,%204Mb,%20v1.4.pdf Change-Id: I91dbc4735bf232e0b1dce72c7f06be967d35ebfb Signed-off-by: DanielZhang <danielzhang@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: Add support for XM25RU256CGeorg Gottleuber2024-06-012-0/+43
| | | | | | | | | | | | | | Tested read, write and erase with ch341a_spi programmer (and 1.8V adapter). Test log: https://paste.flashrom.org/view.php?id=3729 Change-Id: I431474a662304d09438e274706d3fc9cfbbe0bd6 Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add XTX XT25F128BRobert Marko2024-06-012-0/+41
| | | | | | | | | | | | | XTX XT25F128B is 128M-bit version of XT25F64B. Tested probe, read, erase and write with FT232H. Datasheet: https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_XTX-XT25F128BSSIGT_C558844.pdf Change-Id: I37084bd66bc7a8f93d6533ab0d67aa2528786299 Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Correct get_flash_region() to use inclusive upper boundsPeter Marheine2024-05-313-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | get_flash_region() emits a struct flash_region, which uses chipoff_t for the start and end addresses of a region. chipoff_t is defined as a valid flash address, so it was wrong to be setting the end address to start + len; this is clearly wrong in the case where there is a single region because setting end to the flash size generates an address that is beyond the end of the chip (due to zero-indexing). This changes the one actual implementation of .get_region in ichspi.c to use inclusive upper bounds, and corrects all callers of get_flash_region() to treat the upper bounds as inclusive. Overall this reduces complexity slightly by removing more downward adjustments by 1 than it needs to add upward adjustments. TEST=on yaviks, `flashrom -V -x` prints equivalent messages about "x region (0xZZZZ..0xZZZZ) is readable" before and after this patch. Change-Id: Ia0ca867aef33b598c2697fc264807fa5e29683ec Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Add clarification to struct flash_region on chipoff_tPeter Marheine2024-05-311-0/+5
| | | | | | | | | | | | | | | | | Although chipoff_t is fairly clearly documented on its own, it seems fairly frequent that developers will treat the end address of a flash region as an exclusive upper bound rather than the inclusive one it should be; for example CB:82496 fixes an incorrect use that affected multiple sites, and CB:73571 stemmed from a similar cause. Add a clarifying comment to call attention to this, to help programmers avoid making similar mistakes in the future. Change-Id: I80b61a87ca31bd5a116224aadb4e211ee6841e1f Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82677 Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/erase: record the opcode for each erasePeter Marheine2024-05-315-58/+157
| | | | | | | | | | | | | | This allows tests to verify that the correct opcode is used when erasing, which is required to unit-test the fix to issue #525 where in some situations an incorrect erase opcode will be used. BUG=https://ticket.coreboot.org/issues/525 Change-Id: I3983fe42c2e7f06668a1bd20d2db7fafa93b8043 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* doc: Link useful section of manpage into Supported programmers indexAnastasia Klimchuk2024-05-302-0/+3
| | | | | | | | Change-Id: I0c8a761626784f31a71a47c2cebff2579ebbe416 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82646 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc: Add doc for supported flash chipsAnastasia Klimchuk2024-05-302-0/+27
| | | | | | | | | Change-Id: I05fb60a4caf2cfb30586fa482687b10638996395 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: Correct feature_bits for MX25L128*Hsuan Ting Chen2024-05-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | In CB:81792 (CL:5471748) we add write-protect support for MX25L12833F, MX25L12835F/MX25L12873F, and MX25L12845E/MX25L12865E. However, that CL contained a bug that it didn't set the feature_bits correctly. We need to add: * Add FEATURE_CFGR and FEATURE_SCUR for MX25L12833F * Add FEATURE_CFGR and FEATURE_SCUR for MX25L12835F/MX25L12873F * Add FEATURE_SCUR for MX25L12845E/MX25L12865E BUG=b:332486637 TEST=In a host connect to ADL-n ChromeOS via servo, with this patch, flashrom -p raiden_debug_spi:target=AP,custom_rst=true ,serial=$(dut-control -o ccd_serialname -p 9996) --wp-status returns correct WP status. TEST=without this patch, returns error with "Cannot read SECURITY: unsupported by chip" Change-Id: I001cde6816bd099317bc9c23904c5fcbe6003241 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82605 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* add gcc-14 -Werror=calloc-transposed-args compatibilityAlexander Goncharov2024-05-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | gcc-14 added a new `-Wcalloc-transposed-args` warning. Documentation says: ``` Warn about calls to allocation functions decorated with attribute alloc_size with two arguments, which use sizeof operator as the earlier size argument and don’t use it as the later size argument. This is a coding style warning. The first argument to calloc is documented to be number of elements in array, while the second argument is size of each element, so calloc (n, sizeof (int)) is preferred over calloc (sizeof (int), n). ``` Let's fix the existing occurrences. Found-by: gcc v14.1.1 20240507 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Change-Id: Icb9842fbc2fa6ad4cd9dc9384c19fd3741eadb2e Reviewed-on: https://review.coreboot.org/c/flashrom/+/82657 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Add documentation for pico-serprogFunkeleinhorn2024-05-251-0/+12
| | | | | | | | | | | | | This commit adds documentation for pico-serprog by stacksmashing: https://github.com/stacksmashing/pico-serprog and its fork by Riku_V: https://codeberg.org/Riku_V/pico-serprog to the serprog overview page. Change-Id: I457dfec52f89997f64b6c276c50b329359d61b77 Signed-off-by: Funkeleinhorn <git@funkeleinhorn.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82229 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for GigaDevice GD25LR256E, GD251R512MERavi Sarawadi2024-05-242-0/+112
| | | | | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST= Flash image using Flashrom Tool flashrom -p raiden_debug_spi -w <test_binary> flashrom -p dediprog -w <test_binary> Also tested by two people on the mailing list: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/TCT534OIVOFZ2HHIJ4LSADQPS27ENCG2/ Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* flashchips: Add support for chip model GD25LF128EVictor Lim2024-05-232-0/+50
| | | | | | | | | | | | | | | Adding GD25LF128E to flashchip.c GD25LF128E: 1.8V 128Mbit, QE default fixed at 1. Datasheet link https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00632-GD25LF128E-Rev1.3.pdf Change-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe Signed-off-by: Victor Lim <vlim@gigadevice.com> Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82332 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Boya B25Q64ASboyesm2024-05-232-0/+39
| | | | | | | | | | | | The B25Q64AS has been tested by ch341a programmer: read, write, erase Datasheet: https://archive.org/details/1912111437-boyamicro-by-25-q-64-assig-c-383793 Change-Id: I05ecf2b118902db974544d86e023a348912371dd Signed-off-by: Malcolm Boyes <boyesmalcolm@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* doc: Add doc for dummyflasherAnastasia Klimchuk2024-05-232-0/+15
| | | | | | | | Change-Id: I1e2039a3dcb958e96c4f1ff7b99a5629c3e83ed1 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82482 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Add support for region 9 and beyond in Meteor Lakeroccochen@chromium.com2024-05-192-20/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Meteor Lake, configuring region access for FREG9 and higher is necessary. This configuration is determined using BIOS_BM registers: BIOS_BM_RAP (Offset 0x118): BIOS Master Read Access Permissions. Each bit [15:0] corresponds to a region [15:0]. A set bit grants BIOS master read access. BIOS_BM_WAP (Offset 0x11c): BIOS Master Write Access Permissions. Each bit [15:0] corresponds to a region [15:0]. A set bit grants BIOS master write/erase access. Move CHIPSET_METEOR_LAKE to the bottom of the ich_chipset list to ensure that all the newer chipsets in the future will use BIOS_BM check by default. BUG=b:319773700, b:304439294 BUG=b:319336080 TEST=On MTL, use flashrom -VV to see correct FREG9 access TEST=On ADL, use flashrom -VV to see not break anything TEST=On APL, use flashrom -VV to see not break anything Change-Id: I1e06e7b3d470423a6014e623826d9234fdebfbf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81357 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark XM25QU256C as tested for probe/read/erase/write.Michał Kopeć2024-05-191-1/+1
| | | | | | | | | | | | | Mark XM25QU256C as tested for probe/read/erase/write. Found in a Clevo V560TU, tested with a CH341a programmer. Flashrom log: https://paste.flashrom.org/view.php?id=3732 Change-Id: Ia9226b71e355d2cc736af0ac4e039e8a3b73a84b Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add support for MXIC MX25L3273FDanielZhang2024-05-171-0/+45
| | | | | | | | | | | | | | | | | The MX25L3273F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25L3273F datasheet is available at the following URL: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8661/MX25L3273F,%203V,%2032Mb,%20v1.2.pdf Change-Id: I4adaaa796d1db34702e7b0ed8e6fb167a3a5f6d7 Signed-off-by: DanielZhang <danielzhang@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips: Add support for MXIC MX25L1636EDanielZhang2024-05-171-3/+10
| | | | | | | | | | | | | | | | | The MX25L1636E has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25L1636E datasheet is available at the following URL: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8596/MX25L1636E,%203V,%2016Mb,%20v1.3.pdf Change-Id: I415e2d6c89d3d59ba44e22753001c6f69421c39d Signed-off-by: DanielZhang <danielzhang@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* erasure_layout: don't copy region buffers if they're null/zero-sizeAlexander Goncharov2024-05-171-24/+30
| | | | | | | | | | | | | | | memcpy() function expects 2nd parameter to be non-null. Make sure that the pointer is non-null before passing it to the function. Also move allocations under if conditions to avoid allocating memory for a potentially 0 size. Found-by: scan-build, clang v17.0.6 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Change-Id: I99aad4119f9c11bea75e3419926cc833bc1f68c5 Reviewed-on: https://review.coreboot.org/c/flashrom/+/81548 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc: Fix index files in Supported HW sectionAnastasia Klimchuk2024-05-162-2/+11
| | | | | | | | | | | | | | | | | | By default toctree in the index file displays full tree of docs with all the nested levels, and it's too much detail. Besides, left side menu displays the tree anyway, so duplication is not needed. Supported hardware section has the deepest nesting out of all other docs. This patch changes high-level index files to only display flat list of next level subtree. On deeper level, full index is displayed. Change-Id: Ia15e9766cce6f19be1e69fbb1236a327ae3d57b3 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82196 Reviewed-by: Sydney <git@funkeleinhorn.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom_udev.rules: Add rule for CH347Nicholas Chin2024-05-131-0/+3
| | | | | | | | | | This allows the CH347 programmer to be used without root permissions. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ia83fa08f6d7c2f449b1a5c0c387c6d4368b99e3a Reviewed-on: https://review.coreboot.org/c/flashrom/+/82162 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for MXIC MX25R2035FDanielZhang2024-05-122-1/+49
| | | | | | | | | | | | | | | | | The MX25R2035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R2035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8696/MX25R2035F,%20Wide%20Range,%202Mb,%20v1.6.pdf Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64 Signed-off-by: DanielZhang <danielzhang@mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom-tester: Include flashrom/src/cmd.rs tests in Cargo workspaceHsuan Ting Chen2024-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure ChromeOS ebuild (ecargo_test) runs all unit tests, including those under flashrom/src/cmd.rs which were previously being skipped due to not being in the default Cargo workspace. By adding flashrom/ to the [workspace] section of Cargo.toml, these tests will now be consistently included when building and testing flashrom-tester on ChromeOS. References: * ebuild of flashrom-tester: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/refs/heads/main/sys-apps/flashrom-tester/flashrom-tester-9999.ebuild * ecarg_test: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/refs/heads/main/eclass/cros-rust.eclass#765 BUG=b:338962302 TEST=(ChromeOS) FEATURES=`test emerge-corsola flashrom-tester` Could see tests like `cmd::tests::decode_io_opt ... ok` TEST=(UPSTREAM) 1. Build flashrom by `meson` 2. Build bindings/rust/libflashrom by `cargo build` 3. Build util/flashrom_tester by `cargo build` `cargo test --workspace` Could see tests like `cmd::tests::decode_io_opt ... ok` Change-Id: Ic23bc35592e6d7d8dd24c71630ea9a2eb2d58573 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82231 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: add Peter Marheine for build systemPeter Marheine2024-05-111-0/+1
| | | | | | | | Change-Id: Ibae0c006b293dad85a9571ec8e7081a6396bc7ce Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82238 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom: Change chip unlock error to warningNikolai Artemiev2024-05-101-1/+1
| | | | | | | | | | | | | | | | | | Failing to disable WP before write/erase doesn't necessarily indicate an error and flashrom doesn't treat it as such. Print a warning instead on an error. BUG=b:336220545 BRANCH=none TEST=build Change-Id: I14c3b55e387443909ca1efab2fc1901f87dd66d6 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82175 Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashrom: Don't throw around "delay 1 second" so lightlyBrian Norris2024-05-101-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Waiting a full second is a very long time, especially when default_delay() chooses to busy-loop. This code has been around for a decade, with vague references to user reports: commit 8ab49e72af8465d4527de2ec37b22cd44f7a1169 Date: Wed Aug 19 13:55:34 2009 +0000 Disallow erase/write for known bad chips so people won't try without a clear understanding Still, this logic does not belong in the high-level library logic, used by all programmers and all chips. If there is a timing issue, it should either be encoded in the appropriate programmer or flashchip timing. However, we don't really know what chips were in use, as the above commit doesn't have any links to reports. So in a feeble attempt at avoiding breaking users here, we also surmise that... * SPI chips weren't all that common in 2009; * I'm mostly motivated by flashrom performance on Chromebooks, were SPI chips (and linux_mtd / BUS_PROG) are the rule; and * SPI chips have precise timing requirements and an appropriate BUSY status. So we guess that this "calm down" magic delay wouldn't be necessary there. Thus, we allow this magic delay only on non-SPI (and non-BUG_PROG, used by linux_mtd for one) buses as a compromise. Now, this change has some (hopefully [1] tiny) chance of regression, so we have the following considerations: 1. emergency_help_message() already provides documentation on how to contact support, in case we need to handle any user-reported regressions. 2. If there is any regression here, it's only in the --verify code; so we can always provide workarounds for testing this, to determine whether this change may have been at fault. For example, something like: flashrom --write /my/new/image.bin --noverify sleep 1 flashrom --read /tmp/bar.bin cmp /my/new/image.bin /tmp/bar.bin If such problems occur, we can collect system/programmer/chip info to try to encode a more targeted delay into the appropriate chip/programmer implementation, and avoid penalizing the entire project like this. 3. We already have (embedded in erase_write()) erase verification that performs no such delay. So depending on the type of timing error that this delay was attempting to cover, we may have some proof that this delay is no longer necessary (or at least, that whatever systems were needing this delay in the first place are no longer caring about flashrom). 4. We've retained the delay for buses that were likely common in 2009 (per the above "feeble attempt"). NB: I avoid using the BUS_NONSPI macro, because I want to exclude any future buses from this workaround, even in the event that the BUS_NONSPI category grows in the future. [1] Famous last words. BUG=b:325539928 TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \ internal Erase_and_Write Fail_to_verify`, TEST=`vpd -i RW_VPD -s foo=bar; vpd -i RW_VPD -l; \ vpd -i RW_VPD -d foo; vpd -i RW_VPD -l` TEST=`elogtool list; elogtool add 0xa7; elogtool list` on (at least) 2 systems: #1: Kukui/Kakadu rev2 - MTD programmer / kernel 5.10.215-24542-g0515a679eb42 / CrOS ~ 15857.0.0 #2: Zork/Dirinboz rev2 - chip name: vendor="Winbond" name="W25Q128.JW.DTR" / BIOS: Google_Dirinboz.13434.688.0 / kernel 5.4.267-21940-g67f70e251a74 / CrOS ~ 15753.43.0 Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/80807 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 03:01:22 +0000