summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* usbdev: Only match requested USB devicesv1.1-rc2Patrick Rudolph2019-06-031-1/+1
| | | | | | | | | | | | | Don't use a device that has the same vendor ID, but a different than requested product ID. Fixes broken dediprog detection with TOMU in use. Change-Id: I08c1c363ce2d6603e46efecc61d3910e02314fca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32892 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog: Disable 4BA completelyv1.1-rc1Nico Huber2019-04-023-0/+18
| | | | | | | | | | | This is an interim solution. We'll have to enable 4BA step-by-step for each dediprog protocol version. Change-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Fix verification with sparse layoutsNico Huber2019-04-023-9/+34
| | | | | | | | | | | | The full verification step was not accounting for sparse layouts. Instead of the old contents, combine_image_by_layout() implicitly assumed the new contents for unspecified regions. Change-Id: I44e0cea621f2a3d4dc70fa7e93c52ed95e54014a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Remove trailing whitespaceElyes HAOUAS2019-03-048-16/+16
| | | | | | | | | Change-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout.c: Remove unused variableArthur Heymans2019-03-041-2/+0
| | | | | | | | | Change-Id: I0c0c085999a12987376d75825fcf43e788a55a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* layout: Add missing stdbool.h includeNico Huber2019-03-041-0/+1
| | | | | | | | | | Change-Id: I9a413d491038b29c832011a738f3b49e029dcf6f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Fix erasing of unaligned regionsNico Huber2019-03-041-3/+66
| | | | | | | | | | | | | | | | | | The erase (-E) feature is somehow a brute force method, but still, if we are given a region to erase, we should make sure to restore surrounding data if the erase block expands beyond the region. It shares a lot of code with the write path. Though, experiments with common functions have shown that it would make the whole function even harder to read. Maybe we could add some abstraction if we ever need similar code on a third path. Change-Id: I5fc35310f0b090f218cd1d660e27fb39dd05c3c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Fix several -Wno-implicit-fallthrough warningsRichard Hughes2019-02-114-3/+9
| | | | | | | | | | | | GCC is picky about the comment being where the break should go. Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix one more -Wmissing-field-initializers warningRichard Hughes2019-02-031-1/+3
| | | | | | | | | | | | | Fixes: ichspi.c: In function ‘ich_init_spi’: ichspi.c:1707:9: warning: missing initializer for field ‘component’ Change-Id: Iee5728167963fece24822ad2e3ab7bd9d444b42c Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/31224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix a trivial calloc warningRichard Hughes2019-02-031-1/+1
| | | | | | | | Change-Id: Id457c15555a6ca6333474601f92982446afa40ab Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/31223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wno-missing-field-initializers warningsRichard Hughes2019-02-033-2/+8
| | | | | | | | Change-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wold-style-declaration warningsRichard Hughes2019-02-034-5/+5
| | | | | | | | Change-Id: Iffe5e652779a13ee7f64696fb5df4a781fe9a632 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* buspirate_spi: Fix a missing error check during _init()Richard Hughes2019-01-051-0/+2
| | | | | | | | Change-Id: I17c6737853bf311b3f7aa9bfb10b54ce19e95ecc Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix a tiny memory leak in the CLI toolRichard Hughes2019-01-051-0/+1
| | | | | | | | Change-Id: Iec696cb15dcf437f08e1e4f2a5a1faa0df6fd081 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add initial J-Link SPI programmerMarc Schink2019-01-056-1/+592
| | | | | | | | | | Tested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V. Change-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e Signed-off-by: Marc Schink <flashrom-dev@marcschink.de> Reviewed-on: https://review.coreboot.org/c/28087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* linux_spi: Hardcode default spispeed of 2MHzNico Huber2018-12-221-10/+13
| | | | | | | | | | | | Leaving the `linux_spi` driver's unknown default is almost never what we want and resulted in many support requests since Raspbian switched to a default that is too high for most applications. Change-Id: I9361b7c1a1ab8900a619b06e1dae14cd87eb56c2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* chipset_enable.c: Mark Intel C224 as DEPTristan Corrick2018-12-221-1/+1
| | | | | | | | | | | | Tested on a Supermicro X10SLM+-F. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libflashrom.h: Add missing includesNico Huber2018-12-211-0/+2
| | | | | | | | | | <stddef.h> for `size_t` and <sys/types.h> for `off_t`. Change-Id: Ifc84dfe2a06633321d0abd364bdea1216925a779 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* fmap: Fix length calculation in error messageNico Huber2018-12-211-1/+1
| | | | | | | | Change-Id: Ie0f448970de6a7829f304448e0835eaeb7d103a3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog: Fix small, unaligned readsNico Huber2018-12-061-4/+4
| | | | | | | | | | | | | | | This never was a use case until now but the `--fmap` code makes it obvious: Unaligned reads that were smaller than the `chunksize` here, were extended without considering the length of the buffer read into. With that fixed we run into the next problem: dediprog_spi_bulk_read() shouldn't report an error when an empty read is unaligned. Change-Id: Ie12b62499ebfdb467d5126c00d327c76077ddead Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable.c: Mark Intel PM55 as DEPAngel Pons2018-11-031-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Sanyo LE25FU206/A and LE25FU106BAngel Pons2018-11-012-0/+103
| | | | | | | | | | | As per user `The_Raven Raven` on the mailing list. Since the added values had some inconsistencies, the chips are marked as untested. Change-Id: I6c26aafdca232110986334e85297d73d513600dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel H81 as DEPTristan Corrick2018-11-011-1/+1
| | | | | | | | | | | | Tested on an ASRock H81M-HDS. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add IS25LP256 and IS25WP256David Hendricks2018-10-302-0/+102
| | | | | | | | | | | Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q256JV supportDavid Hendricks2018-10-292-1/+49
| | | | | | | | | | | | | | Similar to W25Q256FV, but it supports the native 4BA page program instruction (12h). Note that the variant with QE enabled by default shares the device ID of the W25Q256FV. Tested using a Raspberry Pi. Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/29305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* dmi: Remove nonsense guard; Makefile handles itNico Huber2018-10-231-4/+0
| | | | | | | | Change-Id: If4216be1f9ed308e4580c36d0356480e637ffc82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* flashchips: Mark MX25L25635F as testedKasper Revsbech2018-10-231-1/+1
| | | | | | | | | | As reported by Kasper Revsbech on 2018-10-19. Change-Id: Icf05288c4e7e34af2e3f4b951457df695078847d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support to get layout from fmap (e.g. coreboot rom)Arthur Heymans2018-10-237-10/+648
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flashmap, or simply fmap, is a binary data format for describing region offsets, sizes, and certain attributes and is widely used by coreboot. This patch adds support for the fmap data format version 1.1 and adds --fmap and --fmap-file arguments. Using --fmap will make flashrom to search the ROM content for fmap data. Using --fmap-file will make flashrom search a supplied file for fmap data. An example of how to update the COREBOOT region of a ROM: flashrom -p programmer --fmap -w coreboot.rom -i COREBOOT flashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT The fmap functions are mostly copied from cbfstool. Currently it is made mutually exclusive with other layout options until we are more clever about this input. Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ft2232_spi: add an ability to use GPIO for chip selectionSergey Alirzaev2018-10-082-6/+26
| | | | | | | | Change-Id: I6db05619e0d69ad18549c8556ef69225337b1532 Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com> Reviewed-on: https://review.coreboot.org/28911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM65 as DEPAngel Pons2018-10-081-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Toshiba L755 laptop with an Intel HM65. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25U8032EAngel Pons2018-10-072-0/+41
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I422c3d51e5011e081ff6bccff294817c8c1765d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q128.V..WPatrick Rudolph2018-10-052-0/+38
| | | | | | | | | | | Port the code from chromeos flashrom. Tested using W25Q128JVSIM in SPI mode. Change-Id: I38397a0c831407afa21cddca8485664576fce92c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove unneeded whitespaceElyes HAOUAS2018-10-052-2/+1
| | | | | | | | Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark S25FL208K as testedNico Huber2018-10-041-1/+1
| | | | | | | | | | As report by Frédéric Germain on 2017-12-17. Change-Id: I0a7fc10e75f4a675de41e9765525defe2d2640e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ISSI IS25WP064 and IS25WP032Nico Huber2018-10-042-1/+88
| | | | | | | | | | | | The IS25WP064 was tested successfully by Simon Buhrow as reported on 2018-9-4. While we are at it, also add the 32Mbit version which shares the datasheet (as does the already supported 128Mbit version). Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ATMEL AT25SL128AHal Martin2018-10-032-0/+40
| | | | | | | | | Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/26576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Enable native 4BA instructions for Spansion 25FL256SNico Huber2018-10-031-1/+4
| | | | | | | | | Change-Id: I0ffc816ca714ecce5b89b1eaadb5e73ccb38d9ab Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Enable 4BA mode for Spansion 25FL256SNico Huber2018-10-034-8/+12
| | | | | | | | | | | 4BA mode is entered by setting bit 7 for the extended address register. Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add Spansion 25FL256S......0Nico Huber2018-10-033-1/+47
| | | | | | | | | | | | | | | | The Spansion 25SFL256S supports 4BA through an extended address register, a 4BA mode set by bit 7 of that register, or native 4BA instructions. Enable the former only for now. Unfortunately the S25SF256S uses another instruction to write the exten- ded address register. So we add an override for the instruction byte. Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Mark Spansion S25FL128P......0 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | Tested with a Spansion FL128PIF. Change-Id: Ic99eabb67d5bce3910e9275d0056a7cfa8cff36f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Atmel AT45DB081D as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I225984b9e2589713f25d0f9b49eb1c3abdcff3cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q40BW as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | | As per `The_Raven Raven` on the mailing list. The tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW` when the `W25Q40EW` was added. Change-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD040 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: Ied8d07c54f8a222dbe05503f859f82bba27d8336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Sanyo LE25FU406C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I1dba38d03c826a53bff3ddad0aa536032c5532a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD020 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I16d5a207599b434fe52b42709e42f1f32a8e6698 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25Q128C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Tomasz Walach on the mailing list. Change-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark AMIC A25L40PU as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Stefan Szwarnowski on the mailing list. Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Broadwell U Premium as DEPAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | As per Laurent Grimaud on the mailing list. I also have said chipset. Since all ME-enable chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q256.V as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Richard Hughes via the mailing list. Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Macronix MX66L51235 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Nick (cel366) on 2018-05-16 via mailing list. Change-Id: I44363e6755167adbc120444a481b09bb4e1063c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 23:47:18 +0000