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* linux_spi: Use fgets() to read buffer sizeJacob Garber2019-09-241-2/+1
| | | | | | | | | | | | | | | Since fread() returns the number of bytes read, this currently will only check for errors if it returns 0 (i.e. the file was empty). However, it is possible for fread() to encounter an error after reading a few bytes, which this doesn't catch. Fix this by using fgets() instead, which will return NULL if EOF or an error is encountered, and is simpler anyway. Change-Id: I4f37c70e97149b87c6344e63a57d11ddde7638c4 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403824 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* print: Fix vendor string memory leakJacob Garber2019-09-241-0/+1
| | | | | | | | | | | | Freeing this string won't really matter in the incredible case that we run out of memory, but it keeps Coverity happy. Change-Id: I962d2f2227850473b70272bc48b3fc0a0fb11342 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403822 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* linux_mtd: Fix param memory leakJacob Garber2019-09-241-0/+1
| | | | | | | | | | | | extract_programmer_param() stores allocated memory in param, so make sure it is freed at the end of the function. Change-Id: I363e66b49c1ed4034ac058b94a938c8bb197e048 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403823 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* internal: Fix board vendor and model memory leaksJacob Garber2019-09-243-17/+34
| | | | | | | | | | | | | The board vendor and model are sometimes specified as arguments during an internal flash, so make sure they are freed at the end of initialization. Change-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1230664, 1230665 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ichspi: Replace default JEDEC_BE_D8 with JEDEC_SEDavid Hendricks2019-09-241-1/+1
| | | | | | | | | | | | | | This aligns the upstream master branch with chromium's. On-the-fly opcode reprogramming is supported by both branches so the default opcode shouldn't matter. Review URL: http://codereview.chromium.org/3239001 Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64 Signed-off-by: Mayur Panchal <panchalm@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Add W25Q128.V..M printlock attributeAlan Green2019-09-241-0/+1
| | | | | | | | | | | | Add a printlock attribute for the Winbond W25Q128.V..M chip. The printlock attributes matches the ChromiumOS repo's definition of this chip. Signed-off-by: Alan Green <avg@google.com> Change-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Mark W25Q40EW as TESTED_PREWAlan Green2019-09-241-1/+1
| | | | | | | | | | | | | | Mark Winbond W25Q40EW as TESTED_PREW. The Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS repository. ChromiumOS has the same defintion for this chip as this repo, except that ChromiumOS does not have FEATURE_OTP. Signed-off-by: Alan Green <avg@google.com> Change-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Add GD25Q256D from downstreamAlan Green2019-09-242-0/+39
| | | | | | | | | | | | | Take definition of GD25Q256D from ChromiumOS repository. This chip was added in `commit 0c38355c` by dlaurie@google.com 2019-03-17. Signed-off-by: Alan Green <avg@google.com> Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/35480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom.h: Add types not included in all projectsMario Limonciello2019-09-241-0/+2
| | | | | | | | | | Add <stdbool.h> and <stdint.h> to allow compilation in fwupd. Signed-off-by: Mario Limonciello <mario.limonciello@dell.com> Change-Id: Ib48ddc6412f82677f43e445346dc64ccfadf2423 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* flashchips.c: Mark EN29F002(A)(N)B as tested +EWAlan Green2019-09-181-1/+1
| | | | | | | | | | | | | | | Mark EN29F002(A)(N)B as tested for erase and write. This chip was marked tested in the Chromium (downstream) repo change 98d917cfba55b68516cdf64c754d2f36c8c26722 "Add a bunch of new/tested stuff and various small changes 8" TEST=Build and run flashrom -L Signed-off-by: Alan Green <avg@google.com> Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Identify MX25L25645G partAlan Green2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | Apply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d, "flashrom: Identify MX25L25645G part" from chris_zhou@compal.corp-partner.google.com 2019-04-13. Change description was: """ MX25L25635F and MX25L25645G have the same chips identify. Add MX25L25645G to the name of the part so that it doesn't confused people. """ Signed-off-by: Alan Green <avg@google.com> Change-Id: I317345b4753cfc46fdca8f673a0591e33b62138b Reviewed-on: https://review.coreboot.org/c/flashrom/+/35091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add GD25Q127C name to the GD25Q128C entryAlan Green2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | Renamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128. According to downstream (ChromiumOS) change 4216ba3d0fbd1804a71002b9c17e0b04029a03f1 "flashchips: Add GD25Q127C name to the GD25Q128C entry", the 127C chip is replacement for the 128C chip. I have confirmed that 127C is newer and that 128C does not appear to be documented on Gigadevice's website or available from Digikey. TEST=Ran flashrom -L Signed-off-by: Alan Green <avg@google.com> Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Put SFDP-capable chip back into positionAlan Green2019-09-171-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Put entry for Unknown SFDP-capable chip back into place at end of file. Change 1f9cc7d89992114c70f7a0545ad9f98701bebe56 "flashchips.c: Sort file by vendor and model" reordered many entries in flashchips.c, including this one. However, the entry for Unknown, SFDP-capable chip should not have been moved before any specific chip entries. As reported by Angel Pons <th3fanbus@gmail.com> at https://review.coreboot.org/c/flashrom/+/33931: """ Oops, this introduced a bug: the SFDP entry is no longer at the end of flashchips.c, so probing on a SFDP-capable Winbond chip results in added noise (flashrom says things about an unknown chip, and then has two definitions for the same chip). """ Signed-off-by: Alan Green <avg@google.com> Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc Reviewed-on: https://review.coreboot.org/c/flashrom/+/35037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom: add querying functions with meson integrationArtur Raglis2019-09-173-1/+187
| | | | | | | | | | | Work based on lukasz.dmitrowski@gmail.com code Change-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f Signed-off-by: Artur Raglis <artur.raglis@3mdeb.com> Signed-off-by: Lukasz Dmitrowski <lukasz.dmitrowski@gmail.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: upstream changes to GD25LQ128Alan Green2019-08-212-3/+3
| | | | | | | | | | | | | | | | | | | | | Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the change from the chromium flashrom repo SHA 6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175) The rationale from that change was: The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but both chips identify in the same manner. Add GD25LQ128D to the name of the part so that it doesn't confused people. Making this name consistent will simplify further merging from the chromium fork. Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable: Mark Intel CM236 and CM246 as DEPNico Huber2019-08-081-2/+2
| | | | | | | | | | | | | | | The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also regression tested on Apollo Lake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Add support for Cannon Lake U PremiumMatt DeVillier2019-08-081-0/+1
| | | | | | | | | | | | | Add support for Cannon Lake U Premium (CFL-U/WHL-U). Same as discrete 300-series CNP PCH. Tested on a WHL-U laptop w/unlocked IFD. Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-085-32/+87
| | | | | | | | | | | | | | | | Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-082-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel(R) 300 Series and Intel(R) C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel(R) 300 Series Chipset Families Platform Controller Hub Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
* flashchips: Add missing MT25Q erase commandsJacob Creedon2019-08-051-0/+18
| | | | | | | | | | | This adds additional 32KiB subsector erase commands 0x5c and 0x52 and an additional bulk erase command of 0x60. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa Reviewed-on: https://review.coreboot.org/c/flashrom/+/34490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Fix N25Q512 bulk eraseJacob Creedon2019-08-051-2/+2
| | | | | | | | | | | The N25Q is a stacked device, so it requires 0xC4 to perform a die erase. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Split MT25Q from N25QJacob Creedon2019-08-051-2/+82
| | | | | | | | | | | | | | | The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q is almost entirely backwards compatible with the N25Q series, however, the MT25Q has additional subsector erase commands available, and there are differences in stacked devices in the higher capacity variants. The N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q devices are set with "Micron" as the vendor. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PREAlan Green2019-08-031-1/+1
| | | | | | | | | | | | | | | | The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other differences in the definition of this chip. This is the only change from the Chromium repo to be upstreamed for AMD chips. Signed-off-by: Alan Green <avg@google.com> Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34534 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* flashchips.c: Mark Intel 82802AB as TEST_OK_PREWAlan Green2019-08-031-1/+1
| | | | | | | | | | | | | | Intel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their SHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork and here in upstream are otherwise substantially similar. There are no other downstream changes for Intel chips to be upstreamed. Signed-off-by: Alan Green <avg@google.com> Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34533 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chipset_enable: Fix recent -Wmissing-field-initializer troubleNico Huber2019-07-311-14/+14
| | | | | | | | Change-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* Fix -Wsign-compare troubleNico Huber2019-07-3132-107/+116
| | | | | | | | | | | Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* cli_classic: Fix Memory leakElyes HAOUAS2019-07-191-0/+5
| | | | | | | | | Found-by: scan-build 7.0.1-8 Change-Id: I84e642b57b95953f376569e443ef8d8eda7bf98f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25: Remove dead incrementElyes HAOUAS2019-07-191-1/+0
| | | | | | | | | | | Value stored in 'pos' is never read. Found-by: scan-build 7.0.1-8 Change-Id: I9a70593f182d7558e71e831fc2b834ac58a25b2a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34404 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* pickit2_spi: Fix "dead" assignmentElyes HAOUAS2019-07-191-2/+8
| | | | | | | | | | | | | | We never read the first 'ret'. Let's check the first 'ret' and exit if it failed. Also, print the version only when the command succeeded. Found-by: scan-build 7.0.1-8 Change-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34403 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25L51245G as known chipHemanth Guruva Reddy2019-07-172-2/+2
| | | | | | | | | | MX25L51245G is identical to handling of MX66L51235F. Change-Id: I964e630197e33d69b199fdfb8816f18e3112bbb1 Signed-off-by: Hemanth Guruva Reddy <meethemanth@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* pickit2_spi: update to libusb1 and drop libusb0 dependencyThomas Heijligen2019-07-104-132/+60
| | | | | | | | | | TESTED: read, write, verify Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add Apollo Lake supportNico Huber2019-07-064-61/+155
| | | | | | | | | | | | | | | It's almost identical to 100 series PCHs and later. There are some additional FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Add Apollo LakeNico Huber2019-07-062-4/+21
| | | | | | | | | | | | It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* flashchips.c: Make .tested lines consistentAlan Green2019-07-051-2/+2
| | | | | | | | | | | | | As per comments on https://review.coreboot.org/c/flashrom/+/33833/, make placement of spaces in .tested attributes with literal definitions consistent. Signed-off-by: Alan Green <avg@google.com> Change-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Sort file by vendor and modelAlan Green2019-07-051-4145/+4148
| | | | | | | | | | | | | | | For self-consistency, and to allow tools to assist with merging the chromium fork of flashrom, sort the entries of flashchips.c. The file is already largely sorted, though deviations have crept in over time. This is a non-clever mostly ASCII-order sorting. It is not intended to be permanent. Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33931 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* layout: Increase max rom layout sizePatrick Rudolph2019-07-041-1/+1
| | | | | | | | | | | | | | | | | | When trying to flash a single FMAP region on VBOOT enabled boards the default of 32 entries is to small to store all regions. Flashrom will bail out with "Cannot add fmap entries to layout - Too many entries." Increase the maximum rom layout size to 128 to support complex FMAPs. Tested on coreboot's UP/squared mainboard using SF600. With this patch it's possible to update a single FMAP region. Change-Id: I68084b08f7b35a162b5f2d3109d82a8b63c194ff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34025 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* flashchips.c: Format SFDP-capable chip entryAlan Green2019-07-041-9/+8
| | | | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, make the definition of SFDP-capable chip more consistent with other definitions. This involves - reordering fields to match both other entries and the definition of struct flashchip. - reformatting comments to make them consistent with other entries. Signed-off-by: Alan Green <avg@google.com> Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Make comment placement consistentAlan Green2019-07-041-1/+2
| | | | | | | | | | | | For consistency, move a comment about an entry from inside the open brace to outside it. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Fix field orderAlan Green2019-07-041-15/+15
| | | | | | | | | | | | | For consistency and in order to allow automated tools to work with flashchips.c, put fields in the same order as they are defined in struct flashchip, in flash.h Signed-off-by: Alan Green <avg@google.com> Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c Reviewed-on: https://review.coreboot.org/c/flashrom/+/33833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips.c: Add comma after every .voltage attributeAlan Green2019-07-041-2/+2
| | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, ensure that every voltage attribute ends with a comma, even if it is the last member in the definition. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* flashchips: Drop dead code of AT26DF321Alan Green2019-07-042-20/+1
| | | | | | | | | | | | | | | The definition for the AT26DF321 has been commented out since it was first added in 2008. The chip now appears to be obsolete, being marked "obsolete" and unstocked at Digikey. It is also only referred to in historical documents on the manufacturer's website (microchip.com). To avoid further bitrot of this dead code, drop it. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: format block_erasers membersAlan Green2019-07-031-54/+102
| | | | | | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, ensure all .block_erasers definitions have consistent formatting: - start with the opening brace on a new line. - ensure end brace indented exactly two tabs. SFDP-capable chip is the one exception to this rule as it has an empty block instead. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33831 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Make end of line comments consistentAlan Green2019-07-021-21/+21
| | | | | | | | | | | | | To allow automated tools to manipulate flashchips.c, make end of line comment formatting more consistent. Specifically, this change moves the comma from end of line to immediately after the field value, before the commment. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: ATMEL->Atmel for consistencyAlan Green2019-07-021-1/+1
| | | | | | | | | | | | Replace the single instance where a vendor name was spelled inconsistently. Signed-off-by: Alan Green <avg@google.com> Change-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e Reviewed-on: https://review.coreboot.org/c/flashrom/+/33829 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Make whitespace consistentAlan Green2019-07-021-98/+101
| | | | | | | | | | | | | | | For consistency, and to make the file amenable to manipulation by tools, use only tabs when indenting. Some previous changes had introduced spaces for indenting. Also ensure that every table entry is separated by a single blank line. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ib2193798cc52641d6c443f8851903c749b31cb74 Reviewed-on: https://review.coreboot.org/c/flashrom/+/33828 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for MX25U25635FDavid Tomaschik2019-06-281-0/+49
| | | | | | | | | | | This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read. Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik <davidtomaschik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* cli_classic: Remove old usage warningsJacob Garber2019-06-281-4/+0
| | | | | | | | | | | | We are at version 1.1 now, and the user interface change in 0.9.6 was to make setting the programmer mandatory. This was done all the way back in 2012, so it is safe to remove these warnings now. Change-Id: If1b379b7b8234d50a2f0a4f522f15820a1a6603c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi: Drop spi_controller typeNico Huber2019-06-2718-80/+1
| | | | | | | | | | Not needed anymore. Drop it fast before it encourages anyone to violate layers again! Change-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33651 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi25: Fix layering violation in probe_spi_rdid4()Nico Huber2019-06-271-20/+5
| | | | | | | | | | | | Move the message to a lower level where we can do a more generic check and don't need internal knowledge of the SPI-master driver. Change-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* tree: Make internal variables staticJacob Garber2019-06-2610-18/+18
| | | | | | | | | | | All these variables are only used in the files they are defined in, so they can be made static. Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 11:55:09 +0000