| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
| |
Signed-off-by: Marc Schink <dev@zapb.de>
Change-Id: I476c649f9db7342688560aac9ee5df056517a028
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Initial support of Microchip MEC1308 Embedded Controller.
BUG=b:156144893
BRANCH=none
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Initial support of ENE LPC interface keyboard controller.
BUG=b:156140422
BRANCH=none
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This spi master allows for programming of a Realtek RTD2142
MST with external SPI flash chip routed via its internal i2c
transport mechanism.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=echo "00000000:0004ffff fw" > layout && \
flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \
flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \
flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \
flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name
Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This adds support for the Parade lspcon usb-c to HDMI protocol
translater part that is i2c-controlled. The support allows the
host to reach the SPI ROM that hangs off the part where it
stores its firmware.
Usage is as follows:
flashrom -p lspcon_i2c_spi:bus=X
where X is the bus number.
BUG=b:148746232
BRANCH=none
TEST=tested with following commands, read/write/erase works good.
flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo;
flashrom -p lspcon_i2c_spi:bus=7 -E;
flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo;
Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Initial check-in of the Raiden debugger programmer.
Squash in,
raiden_debug: Add missing .write_aai cb fn
raiden_debug: greatly improve protocol documentation
BUG=b:143389556
BRANCH=none
TEST=builds
Change-Id: Ifad273a708acea4de797a0808be58960635a8864
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
Change-Id: Iea40da587729f3975a8901d3933e7567805242c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
|
| |
|
|
|
|
|
|
|
|
| |
TESTED: read, write, verify
Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/32213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
|
The fwupd project has to build in all kinds of crazy targets, e.g. for odd
endians, odd instruction sets, and in odd ways, e.g. installing with a prefix
of /app for projects like flatpak. We also have other "robustness" guarantees
and therefore have a comprehensive set of CI tests which enable a lot of
warning flags and run linting and static analysis code like Coverity.
Rather than hack the Makefile I ported the codebase to use Meson.
Meson is a(nother) next-generation build system used by a lot of open source
projects ranging from low level libraries to desktop software. As part of the
port, I also copied the CONFIG_ logic from the makefile, e.g.
Option Current Value Possible Values Description
------ ------------- --------------- -----------
config_atahpt false [true, false] Highpoint (HPT) ATA/RAID controllers
config_atapromise false [true, false] Promise ATA controller
config_atavia true [true, false] VIA VT6421A LPC memory
...
At the moment I'm using the meson port so I can include flashrom as a subproject
to fwupd as distros are not yet shipping libflashrom as a shared library.
Change-Id: I3d950ece2a0568c09985eab47ddab9df1d0c43a2
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/31248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
