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* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-516/+0
| | | | | | | | | | | | Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* NEED_PCI: remove macroThomas Heijligen2022-04-131-2/+0
| | | | | | | | | | The NEED_PCI macro is only used to guard prototypes. This is not needed. Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* libflashrom,linux_mtd: add linux_mtd writeprotect supportNikolai Artemiev2022-04-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a generic framework to allow opaque programmers to implement writeprotect operations and uses the framework to support writeprotect operations on linux MTD device files. The generic framework comprises three new functions in `struct opaque_master` that are called from libflashrom: - wp_write_cfg() - wp_read_cfg() - wp_get_ranges() For linux_mtd, only the read/write functions are implemented. Linux's MTD interface doesn't provide a way to get available ranges, so calling get_wp_ranges() on the linux_mtd master will return FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE. BUG=b:182223106 BRANCH=none TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash TEST=flashrom --wp-enable --wp-range <non-empty> succeeds TEST=flashrom --wp-enable --wp-range <empty> fails as expected TEST=flashrom --wp-disable --wp-range <empty> succeeds TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected TEST=flashrom --wp-status succeeds Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* dmi.c: Hide has_dmi_support global behind methodEdward O'Callaghan2022-04-051-1/+1
| | | | | | | | | | | | | | | | | This allows has_dmi_support to be become static local to just the scope of dmi.c BUG=none TEST=builds Change-Id: Ibded9714998ea6f2e5d4e0512fa7c6b105f9638a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* pcidev: Move pci_dev_find() from internal to canonical placeEdward O'Callaghan2022-03-221-3/+2
| | | | | | | | | | | | | | | | | Also rename to `pcidev_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: Ie21f87699481a84398ca4450b3f03548f0528191 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pcidev: Move pci_card_find() from internal to canonical placeEdward O'Callaghan2022-03-221-2/+1
| | | | | | | | | | | | | | | | | | | Also rename to `pcidev_card_find()` in fitting with pcidev.c helpers. BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* pcidev: Move scandev_inclass logic from internal to pcidevEdward O'Callaghan2022-03-041-1/+1
| | | | | | | | | | | | | | | BUG=b:220950271 TEST=```sudo ./flashrom -p internal -r /tmp/bios <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Reading flash... done. ``` Change-Id: I1978e178fb73485f1c5c7e732853522847267cee Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* pcidev: Move pci_get_dev() logic into canonical placeEdward O'Callaghan2022-03-021-0/+1
| | | | | | | | | | | | | | | BUG=b:220950271 TEST=```sudo ./flashrom -p internal --flash-size <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. 16777216 ``` Change-Id: Id9ce055d5e5d347520ec5002b8c6548e60eaa0a7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* pcidev: Avoid internal programmer relying on pacc globalEdward O'Callaghan2022-02-241-0/+2
| | | | | | | | | | | | | | | | | | | Make progress towards the goal of removing pacc from global state as noted in the FIXME of programmer.h BUG=b:220950271 TEST=```sudo ./flashrom -p internal --flash-size <snip> Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. 16777216 ``` Change-Id: Id83bfd41f785f907e52a65a6689e8c7016fc1b77 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Add Elkhart Lake supportWerner Zeh2022-02-041-0/+1
| | | | | | | | | | | | | | | | Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add mediatek_i2c_spi interfaceNeill Corlett2022-02-011-0/+1
| | | | | | | | | | | | | | | Add a spi_master interface supporting MediaTek MST9U ISP mode. Autodetect the bus type via I2C_FUNC_I2C, and use the appropriate read/write commands, in case the MST9U is attached to smbus. TEST=Successfully programmed SPI on test hardware. Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820 Signed-off-by: Neill Corlett <corlett@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* physmap: rename to hwaccess_physmap, create own headerThomas Heijligen2021-12-221-8/+0
| | | | | | | | | | Line up physmap with the other hwaccess related code. Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess physmap: move x86 msr related code into own filesThomas Heijligen2021-12-221-3/+1
| | | | | | | | | | | | Allow x86 msr related code to be compiled independent from memory mapping functionality. This enables for a better selection of needed hardware access types. Change-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* hwaccess: move x86 port I/O related code into own filesThomas Heijligen2021-12-221-1/+0
| | | | | | | | | | | | Allow port I/O related code to be compiled independent from memory mapping functionality. This enables for a better selection of needed hardware access types. Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess.c: move function declarations from programmer.h to hwaccess.hThomas Heijligen2021-11-071-33/+0
| | | | | | | | | | | | Move declarations for functions implemented in hwaccess.c from programmer.h to hwaccess.h. Change-Id: I075fd86211c766ae3d5f29c76adbd7c5b9bdbd80 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58865 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mec1308: remove MEC1308 EC programmerVictor Ding2021-09-221-1/+0
| | | | | | | | | | | | | | | | | Best efforts were made to upstream older Chromebook support for good intentions for folks interested. However, we no longer have the hardware available to test and maintain the code as the hardware is now end of life. Therefore the code state has sadly fallen into a unknown state. BUG=none BRANCH=none TEST=builds and ninja test passes Signed-off-by: Victor Ding <victording@google.com> Change-Id: I535b6380846734c999474519e9e60a73eb6a2ec4 Reviewed-on: https://review.coreboot.org/c/flashrom/+/56476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ene_lpc: remove ENE LPC programmerVictor Ding2021-09-221-1/+0
| | | | | | | | | | | | | | | | | Best efforts were made to upstream older Chromebook support for good intentions for folks interested. However, we no longer have the hardware available to test and maintain the code as the hardware is now end of life. Therefore the code state has sadly fallen into a unknown state. BUG=none BRANCH=none TEST=builds and ninja test passes Signed-off-by: Victor Ding <victording@google.com> Change-Id: I3f40db22c42c04ce029c4defd837e05ebb550c9b Reviewed-on: https://review.coreboot.org/c/flashrom/+/56475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* par_master: Add shutdown function in par_master structAnastasia Klimchuk2021-08-301-0/+1
| | | | | | | | | | | | | | | | | | With this, register_par_master can take care of register_shutdown as well, and every par master only needs to call register_par_master instead of calling both register_par_master and register_shutdown. Next patches in the chain convert par masters to use new API. BUG=b:185191942 TEST=builds and ninja test Change-Id: I0fee15d548cdd16678e551eeb351e659812ddf76 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* opaque_master: Add shutdown function in opaque_master structAnastasia Klimchuk2021-08-171-0/+1
| | | | | | | | | | | | | | | | | | With this, register_opaque_master can take care of register_shutdown as well, and every opaque master only needs to call register_opaque_master instead of calling both register_opaque_master and register_shutdown. Next patches in the chain convert opaque masters to use new API. BUG=b:185191942 TEST=builds and ninja test from CB:56413 Change-Id: I34183e6bafc787eec54ee4a26b73a40803f3ce99 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi_master: Add shutdown function in spi_master structAnastasia Klimchuk2021-08-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | With this, register_spi_master can take care of register_shutdown as well, and every spi master only needs to call register_spi_master instead of calling both register_spi_master and register_shutdown. Testing: In dummyflasher, comment out free(data) in shutdown. Test fails with error: ../dummyflasher.c:949: note: block 0x55e0727a6e40 allocated here ERROR: dummy_init_and_shutdown_test_success leaked 1 block(s) Means, shutdown function is invoked for drivers with "old" API (so, transitioning from old to new API is not breaking anything). Next patches in the chain converts spi masters to use new API. BUG=b:185191942 TEST=builds and ninja test Change-Id: I2dc80dceca2f8204bcd0dad1f51753d7e79f1af5 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer.h: sort programmer entries alphabeticallyThomas Heijligen2021-06-201-29/+29
| | | | | | | | Change-Id: Ie419eac2719aceb3aea803fac8ce85de294c88e5 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55495 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer.h: remove compile guard from programmer driversThomas Heijligen2021-06-111-187/+43
| | | | | | | | | | | | The definition of external structs doesn't have to be guarded. See discussion under review.coreboot.org/52946. Change-Id: I01e6a785269c3e0bd648eeaee217a7a855ab0853 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* enum programmer: not needed anymore. RemoveThomas Heijligen2021-06-101-121/+0
| | | | | | | | | Change-Id: I53cdb160616911a4beea6b5e8e56d582621818a4 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer_init: use struct programmer_entry*Thomas Heijligen2021-06-101-1/+1
| | | | | | | | Change-Id: Iacf0f25abc94a84c5d52c8d69a3e8640817b060a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer_table: move each entry to the associated programmer sourceThomas Heijligen2021-06-101-71/+40
| | | | | | | | | Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer_table: convert entries to pointersThomas Heijligen2021-06-091-1/+1
| | | | | | | | | | Allows us to move the individual entries into their respective driver files. Change-Id: Ifbb0ee4db5a85b1cd2afeafe4dca838579f79878 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer_table: add table size constantThomas Heijligen2021-06-091-0/+1
| | | | | | | | | | | | Makes the array size known to other compilation units. Change-Id: Idacb4b7b0dd98af8bc7cbecf567d33daafb4b24d Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55116 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* bitbang: Extend bitbang_spi_master functions to accept spi dataAnastasia Klimchuk2021-06-031-8/+8
| | | | | | | | | | | | | | | | This way every bitbang spi master has access to its own spi data, and can use this data in all its functions. This patch only changes the signatures of functions. BUG=b:185191942 TEST=builds Change-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* bitbang: Extend register_spi_bitbang_master() API with spi dataAnastasia Klimchuk2021-06-031-1/+1
| | | | | | | | | | | | | | | This allows the users of register_spi_bitbang_master() API to pass their spi data into the API, and then the data can go further, into register_spi_master() API. BUG=b:185191942 TEST=builds Change-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer: Smoothen register_opaque_master() APIAnastasia Klimchuk2021-05-231-1/+1
| | | | | | | | | | | | | | | | It was impossible to register a const struct opaque_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. BUG=b:185191942 TEST=builds Change-Id: Id3adb4cf04ae04dbe87ddb96f30871cb5f7c8ff0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54170 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer: Smoothen register_par_master APIAnastasia Klimchuk2021-05-231-1/+1
| | | | | | | | | | | | | | | It was impossible to register a const struct par_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. BUG=b:185191942 TEST=builds Change-Id: I95bc92f6c54c5bcdac1c522ca87054aaffed0f40 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Fix up handling of IFD chipsetsAngel Pons2021-05-201-1/+1
| | | | | | | | | | | | | When `CHIPSET_400_SERIES_COMET_POINT` got added, the `chipset_names` table was not updated. Add the missing entry and reorder it to be next to `CHIPSET_300_SERIES_CANNON_POINT` for consistency. Change-Id: I4f4b31ecf91c432a2e82a92e274cb91ac166e635 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
* Add Gemini Lake supportAngel Pons2021-05-161-0/+1
| | | | | | | | | | | The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer: Smoothen register_spi_master() APINico Huber2021-05-131-1/+1
| | | | | | | | | | | | | It was impossible to register a const struct spi_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer.h: Convert anon union to anon structEdward O'Callaghan2021-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Convert the anon union of registered masters in the mst field of the flashctx to a anon struct. If we are going to dereference a pointer there in an undefined way we should crash and not plow ahead with invalid memory. The user of the registered_masters type is therefore responsible for querying the buses_supported field before attempting to dereference a ptr field in the anon struct. BUG=b:175849641 TEST=`flashrom -p internal --flash-name` Change-Id: I576967a8599b923c902e39f177f39146291cc242 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50246 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Daniel Campello <campello@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer.h: remove unused declarationAlan Green2021-01-221-1/+0
| | | | | | | | | | | | | | Removes unused declaration of noop_shutdown(). The implementation was removed in 386cc556a4 and this declaration ought to have been removed at the same time. Signed-off-by: Alan Green <avg@google.com> Change-Id: I7599ace08f3635251a80612df4b4d29001f81d35 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49800 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Drop const from opaque data ptr in master definitions [alt]Edward O'Callaghan2021-01-171-3/+3
| | | | | | | | | | | | | | | | | | The opaque data pointer need not necessarily have constant data for the life-time of the specific master. This is because the data field purpose is for the master to use as it sees fit for managing its own internal state and therefore we should not constrain this as being RO data at init time. BUG=none BRANCH=none TEST=builds Change-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashrom.c: Correct "raiden_debug_spi" drv nameEdward O'Callaghan2020-11-301-1/+1
| | | | | | | | | | | | | | | Unfortunately raiden_debug was upstreamed with a slightly incorrect name of "raiden_debug" whereas in ChromiumOS it is known as "raiden_debug_spi" and so correct this to align. This avoids confusion and divergence for a unified future. Change-Id: I0eca35863403c5d4adbe19b31801e8dfa072006f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug: Rename with '_DEBUG_SPI' suffixEdward O'Callaghan2020-11-281-2/+2
| | | | | | | | | | | | Unfortantly raiden_debug was upstreamed with a misnaming of the CONFIG_ make param that introduces unnecessary divergence. Rename to 'CONFIG_RAIDEN_DEBUG_SPI' as-is downstream. Change-Id: I07c03647c329286bb223e4dae4665704e508db2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* programmer.h,c: Drop dead noop_chip_writeb() fnEdward O'Callaghan2020-11-241-1/+0
| | | | | | | | | | | | | | Drop dead code. BUG=none BRANCH=none TEST=`git grep noop_chip_writeb` Change-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* programmer.h: Reorder MEC1308 and ENE_LPC enumeratorsEdward O'Callaghan2020-11-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Programmer enumerators and their corresponding programmer_table entries need to be aligned. This was not the case for MEC1308 and ENE_LPC. Their configs were not enabled by default until commit 26fde5b0b067 ("ene_lpc,mec1308: Fix entry-points to be explicit")/CL:2488823, allowing this issue to go unnoticed. The particular symptom of the mismatch was internal_init() trying to init linux_mtd instead of linux_spi. BUG=b:172668501 TEST=flashrom -p host on gale BRANCH=None Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52 Original-Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47353 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Victor Ding <victording@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+1
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Add MEC1308 EC programmerVictor Ding2020-08-201-0/+8
| | | | | | | | | | | | | Initial support of Microchip MEC1308 Embedded Controller. BUG=b:156144893 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add ENE LPC programmerVictor Ding2020-08-201-0/+8
| | | | | | | | | | | | | | Initial support of ENE LPC interface keyboard controller. BUG=b:156140422 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d Reviewed-on: https://review.coreboot.org/c/flashrom/+/44580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-041-0/+8
| | | | | | | | | | | | | | | | | | | | | This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-4/+4
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 19:42:23 +0000