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* realtek_mst_i2c_spi.c: Consolidate shifts to the one fnEdward O'Callaghan2021-01-011-9/+8
| | | | | | | | | | | | | | | | To avoid further incorrect mappings ensure all the shifting happens within realtek_mst_i2c_spi_map_page() itself. BUG=none BRANCH=none TEST=builds Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Suggested-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Don't depend on int overflowsEdward O'Callaghan2021-01-011-6/+6
| | | | | | | | | | | | | | | | | Be explicit to mask the first byte after the shifts as highlighted by Angel Pons. BUG=none BRANCH=none TEST=builds Change-Id: I7d1215678094d709e79b8f8c96aa3810586cd72e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Spotted-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48974 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix writeShiyu Sun2020-12-291-2/+3
| | | | | | | | | | | | | | | Update the PAGE_SIZE to 128 as fix r/w on different devices, also fix the write page mapping for it. BUG=b:147402710 TEST=build and run flashrom to read&write on multiple devices Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Add ISP mode checkShiyu Sun2020-12-231-3/+14
| | | | | | | | | | | | | | Check ISP mode before doing reset and add waiting after the enter ISP mode command. BUG=None TEST=build and run mst commands Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f Reviewed-on: https://review.coreboot.org/c/flashrom/+/48662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* realtek_mst_i2c_spi.c: Introduce ISP enter paramShiyu Sun2020-10-241-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to avoid attempt entering ISP mode multiple times. The ISP mode can only exit after a reset, so once the reset MCU parameter is set to 0, the device will not able to exit from ISP mode and hence shouldn't enter ISP again on the next operation. Without exit ISP mode, the device data, like firmware version, will not show the correct value, this param will also help to identify this situation. BUG=b:152558985,b:148745673 BRANCH=none TEST=build and run: $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=1 \ -l layout -i PARTITION1:fw -w $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=0 \ -l layout -i FLAG1:flag -w then either reset computer to allow update to take effect, or: $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=1,enter-isp=0 \ --flash-size to trigger the update. Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I58931ac8b42ab55829f102d243aea6fcfd632e3e Reviewed-on: https://review.coreboot.org/c/flashrom/+/46623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* realtek_mst_i2c_spi.c: Trigger gpio 88 toggle down after writeShiyu Sun2020-10-231-2/+1
| | | | | | | | | | | | | BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I1407714e1bb4cf2472090bae8a613c7103a5938c Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46448 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Update GPIO pin 88 toggle functionShiyu Sun2020-10-141-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Here we provide a helper function to allow indexing MCU configuration registers. The 0x9F port allows access to these MCU configuration registers followed by the high and then low bytes of the register address we wish to index written into 0xF5 or 0xF4 respectively, a read or write can then be made via 0xF5. For the configuration of GPIO pins on the chip, there are two relevant register address, 0x104F for pin direction (sink input or push-pull in-out) configuration and 0xFE3F for pin data values (1 to push-pull and 0 to sink). The reference design uses GPIO 88 to strap the write protection pin and so we provide a function that allows the call site to toggle this state and therefore de-assert hardware write protection of the external spi flash. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds && verified the write protection get disabled. Change-Id: I1aed0086f917e31bebb51857ad5cce138158fe82 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46089 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Fixup get_params() err ctrl flowEdward O'Callaghan2020-10-021-5/+4
| | | | | | | | | | | | | Ensure that when bus number and reset params are specified at the same time are both correctly parsed by get_params(). Also renames the goto err cleanup path to make it clear. Change-Id: Icb45b1ab39181b0f1a2dec1cce549d30db984936 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Spotted-by: Shiyu Sun <sshiyu@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45944 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Introduce MCU reset paramEdward O'Callaghan2020-10-021-5/+26
| | | | | | | | | | | | Modify the spi master as to not automatically reset the MCU on tear-down unless explicitly stated by a param. Change-Id: Ib70bf7399e7541f30b6905cdb950a6fb7b74ae18 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45674 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove reset from init fnEdward O'Callaghan2020-10-021-5/+0
| | | | | | | | | | | | | | Remove MCU reset on init as this was only introduced when MCU fw requirements for correct flashing were unknown however it turns out no MCU fw is required to flash and so no MCU reset should occur upon initialization. Change-Id: Ia03f94effc4b720964638c032bbde5acfb13960d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45896 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove dead codeEdward O'Callaghan2020-05-071-33/+0
| | | | | | | | | | | | | | | Turns out the MST likely doesn't need these so-called defaults to be written for the purposes of spi flashing. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: Ieb938cf0805b22692d61db23795208c9be962b60 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix cmd timeout issueEdward O'Callaghan2020-05-071-8/+12
| | | | | | | | | | | | | | | | | | | | | Chip erasures take much longer than sector and bank erasures. Allow the wait loop helper to multiply the max timeout in this very specific case while quickly timeout for other ops that are expected to be shorter. V.2: Fix nonsense fall though warn-err BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo (cycle).. Change-Id: I4a36aa3101827e69eb244775d25bbb476d4bb780 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_write256() as documentedEdward O'Callaghan2020-05-061-22/+50
| | | | | | | | | | | | | | | | | | | | | | | | | Turns out broken erasures highlighted some of the issues in the write256 implementation. After a fair amount of time deciphering scarce documentation details a correct implementation was finally derived. V.2: Rename 'start_program() -> execute_write()' to clarify the intention and not to overload the term 'program' since the MST actually runs a 'program' itself. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: If61ff95697f886d3301a907b76283322c39ef5c7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasuresEdward O'Callaghan2020-05-061-9/+40
| | | | | | | | | | | | | | | | | | | | Before issuing SPI opcodes into 0x61 the top three BITS of 0x60 need to be carefully crafted. Correctly craft these in the case of SPI erasures and document this registers expectations. Clean up remaining debug comments while we are here. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Define some register namesEdward O'Callaghan2020-05-051-6/+14
| | | | | | | | | | | | | | | | Try to document some of the register magics with plausible names for readability. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-041-0/+437
This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 08:54:54 +0000