From 62027c8e3733f891637fa9c4415af61f997e326c Mon Sep 17 00:00:00 2001 From: Jan Samek Date: Wed, 8 Jan 2020 12:35:14 +0100 Subject: chipset_enable: add PCI ID for APL-I (Broxton) Change-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324 Signed-off-by: Jan Samek Signed-off-by: Henning Schild Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- chipset_enable.c | 1 + 1 file changed, 1 insertion(+) diff --git a/chipset_enable.c b/chipset_enable.c index 632679c20..d56a5470b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2052,6 +2052,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, -- cgit v1.2.3