From 88ee040ab98a1ffa0c7d8faf6aac1187500e4974 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 14 Sep 2013 23:37:01 +0000 Subject: Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Register locations are different from ICH6, but otherwise appear to have identical bit specifications and defaults. Corresponding to flashrom svn r1748. Signed-off-by: Kyösti Mälkki Acked-by: Stefan Tauner --- chipset_enable.c | 34 ++++++++++++++++++++++------------ flashrom.8.tmpl | 2 +- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 4cdf9a205..c85db7337 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -323,7 +323,7 @@ static int enable_flash_ich0(struct pci_dev *dev, const char *name) return enable_flash_ich(dev, name, 0x4e); } -static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name) +static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { uint32_t fwh_conf; uint8_t fwh_sel1, fwh_sel2, fwh_dec_en_lo, fwh_dec_en_hi; @@ -332,11 +332,20 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name) int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; - /* Register map from ICH6 onwards. */ - fwh_sel1 = 0xd0; - fwh_sel2 = 0xd4; - fwh_dec_en_lo = 0xd8; - fwh_dec_en_hi = 0xd9; + if (ich_generation >= CHIPSET_ICH6) { + fwh_sel1 = 0xd0; + fwh_sel2 = 0xd4; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + } else if (ich_generation >= CHIPSET_ICH2) { + fwh_sel1 = 0xe8; + fwh_sel2 = 0xee; + fwh_dec_en_lo = 0xf0; + fwh_dec_en_hi = 0xe3; + } else { + msg_perr("Error: FWH decode setting not implemented.\n"); + return ERROR_FATAL; + } idsel = extract_programmer_param("fwh_idsel"); if (idsel && strlen(idsel)) { @@ -441,11 +450,12 @@ idsel_garbage_out: static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) { - /* - * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and - * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and - * FB_DEC_EN2. - */ + int err; + + /* Configure FWH IDSEL decoder maps. */ + if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) + return err; + internal_buses_supported = BUS_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -475,7 +485,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_c int err; /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, name)) != 0) + if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) return err; /* If we're called by enable_flash_ich_dc_spi, it will override diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 9f8af039c..b507a9727 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -397,7 +397,7 @@ syntax. If this leads to erase or write accesses to the flash it would most probably bring it into an inconsistent and unbootable state and we will not provide any support in such a case. .sp -If you have an Intel chipset with an ICH6 or later southbridge and if you want +If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the .sp -- cgit v1.2.3