From 9f90f4c01b6b22aa425e8e8abc34ef76b422c507 Mon Sep 17 00:00:00 2001 From: Nikolai Artemiev Date: Tue, 3 Nov 2020 17:19:52 +1100 Subject: chipset_enable.c: mark "Broadwell U Base" as DEP Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets. BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Angel Pons --- chipset_enable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chipset_enable.c b/chipset_enable.c index 7c98798ce..9205d0e5e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2002,7 +2002,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, -- cgit v1.2.3