From a43e44b6abbe8381be3f3dd20a430973cf8b8ab5 Mon Sep 17 00:00:00 2001 From: sibradzic <5964548+sibradzic@users.noreply.github.com> Date: Fri, 14 Feb 2020 17:15:02 +0900 Subject: ft2232_spi: Fix broken GPIOL cs_bits state (#126) This only sets 3rd CS# bit be asserted during read/write operations. Tested and confirmed working on 4232H & PicoTap ft2232 programmers against MX25R6435F & S25FL128S chips. Signed-off-by: Samir Ibradzic Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- ft2232_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 3e4dc9e44..1a5b2feb4 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -495,7 +495,7 @@ static int ft2232_spi_send_command(struct flashctx *flash, */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ buf[i++] = pindir; if (writecnt) { -- cgit v1.2.3