From c4d3efbffdf22367c71ec712c828969aafadab54 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 30 Sep 2018 19:39:41 +0200 Subject: chipset_enable.c: Mark Broadwell U Premium as DEP As per Laurent Grimaud on the mailing list. I also have said chipset. Since all ME-enable chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/28817 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- chipset_enable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chipset_enable.c b/chipset_enable.c index 566b1fb07..4b28924e7 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1896,7 +1896,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, - {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc3, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, -- cgit v1.2.3