From ea0c093246fbaba9ab89348400ba4e99032aa4e0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 4 Jul 2019 17:34:16 +0200 Subject: chipset_enable: Mark Intel CM236 and CM246 as DEP The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also regression tested on Apollo Lake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/flashrom/+/34073 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- chipset_enable.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 1636f7c0b..f02ba87e6 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2009,7 +2009,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, {0x8086, 0xa14d, B_S, NT, "Intel", "QM170", enable_flash_pch100}, {0x8086, 0xa14e, B_S, NT, "Intel", "HM170", enable_flash_pch100}, - {0x8086, 0xa150, B_S, NT, "Intel", "CM236", enable_flash_pch100}, + {0x8086, 0xa150, B_S, DEP, "Intel", "CM236", enable_flash_pch100}, {0x8086, 0xa151, B_S, NT, "Intel", "QMS180", enable_flash_pch100}, {0x8086, 0xa152, B_S, NT, "Intel", "HM175", enable_flash_pch100}, {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, @@ -2045,7 +2045,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; -- cgit v1.2.3