From eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 15 Oct 2020 19:19:05 +1100 Subject: chipset_enable.c: check return value from rphysmap() call Port from the ChromiumOS fork of flashrom. Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally Reviewed-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/flashrom/+/67867 Reviewed-by: Felix Singer --- chipset_enable.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/chipset_enable.c b/chipset_enable.c index 0dfe26756..5195b9503 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1002,6 +1002,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). -- cgit v1.2.3