From 372eeb5710bccae7dfe3ab2819fed08623c4b24c Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Tue, 4 Dec 2007 21:49:06 +0000 Subject: Various coding style fixes, constification, fixed typos Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Corresponding to flashrom svn r162 and coreboot v2 svn r2997. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann --- chipset_enable.c | 141 +++++++++++++++++++++++-------------------------------- 1 file changed, 59 insertions(+), 82 deletions(-) (limited to 'chipset_enable.c') diff --git a/chipset_enable.c b/chipset_enable.c index 87929f58f..7eecf0982 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -34,12 +34,14 @@ #include #include "flash.h" -static int enable_flash_ali_m1533(struct pci_dev *dev, char *name) +static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; - /* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and - 0xFFFE0000-0xFFFFFFFF ROM select enable. */ + /* + * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and + * 0xFFFE0000-0xFFFFFFFF ROM select enable. + */ tmp = pci_read_byte(dev, 0x47); tmp |= 0x46; pci_write_byte(dev, 0x47, tmp); @@ -47,24 +49,28 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_sis630(struct pci_dev *dev, char *name) +static int enable_flash_sis630(struct pci_dev *dev, const char *name) { - char b; + uint8_t b; - /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */ + /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ b = pci_read_byte(dev, 0x40); pci_write_byte(dev, 0x40, b | 0xb); - /* Flash write enable on SiS 540/630 */ + + /* Flash write enable on SiS 540/630. */ b = pci_read_byte(dev, 0x45); pci_write_byte(dev, 0x45, b | 0x40); - /* The same thing on SiS 950 SuperIO side */ + /* The same thing on SiS 950 Super I/O side... */ + + /* First probe for Super I/O on config port 0x2e. */ outb(0x87, 0x2e); outb(0x01, 0x2e); outb(0x55, 0x2e); outb(0x55, 0x2e); if (inb(0x2f) != 0x87) { + /* If that failed, try config port 0x4e. */ outb(0x87, 0x4e); outb(0x01, 0x4e); outb(0x55, 0x4e); @@ -99,7 +105,7 @@ static int enable_flash_sis630(struct pci_dev *dev, char *name) * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ -static int enable_flash_piix4(struct pci_dev *dev, char *name) +static int enable_flash_piix4(struct pci_dev *dev, const char *name) { uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ @@ -132,23 +138,19 @@ static int enable_flash_piix4(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl) +/* + * See ie. page 375 of "Intel ICH7 External Design Specification" + * http://download.intel.com/design/chipsets/datashts/30701302.pdf + */ +static int enable_flash_ich(struct pci_dev *dev, const char *name, + int bios_cntl) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but + /* + * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but * just treating it as 8 bit wide seems to work fine in practice. */ - - /* see ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf - */ - old = pci_read_byte(dev, bios_cntl); new = old | 1; @@ -166,17 +168,17 @@ static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl) return 0; } -static int enable_flash_ich_4e(struct pci_dev *dev, char *name) +static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { return enable_flash_ich(dev, name, 0x4e); } -static int enable_flash_ich_dc(struct pci_dev *dev, char *name) +static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { return enable_flash_ich(dev, name, 0xdc); } -static int enable_flash_vt823x(struct pci_dev *dev, char *name) +static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -194,7 +196,7 @@ static int enable_flash_vt823x(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_cs5530(struct pci_dev *dev, char *name) +static int enable_flash_cs5530(struct pci_dev *dev, const char *name) { uint8_t reg8; @@ -224,7 +226,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_cs5536(struct pci_dev *dev, char *name) +static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { int fd_msr; unsigned char buf[8]; @@ -233,15 +235,15 @@ static int enable_flash_cs5536(struct pci_dev *dev, char *name) /* Geode systems write protect the BIOS via RCONFs (cache * settings similar to MTRRs). To unlock, change MSR 0x1808 * top byte to 0x22. Reading and writing to msr, however - * requires instrucitons rdmsr/wrmsr, which are ring0 privileged + * requires instructions rdmsr/wrmsr, which are ring0 privileged * instructions so only the kernel can do the read/write. This * function, therefore, requires that the msr kernel module be * loaded to access these instructions from user space using * device /dev/cpu/0/msr. This hard-coded driver location * could have potential problems on SMP machines since it - * assumes cpu0, but it is safe on the geode which is not SMP. + * assumes cpu0, but it is safe on the Geode which is not SMP. * - * This is probably not portable beyond linux. + * This is probably not portable beyond Linux. */ fd_msr = open("/dev/cpu/0/msr", O_RDONLY); @@ -272,7 +274,7 @@ static int enable_flash_cs5536(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_sc1100(struct pci_dev *dev, char *name) +static int enable_flash_sc1100(struct pci_dev *dev, const char *name) { uint8_t new; @@ -288,16 +290,14 @@ static int enable_flash_sc1100(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_sis5595(struct pci_dev *dev, char *name) +static int enable_flash_sis5595(struct pci_dev *dev, const char *name) { uint8_t new, newer; new = pci_read_byte(dev, 0x45); - /* clear bit 5 */ - new &= (~0x20); - /* set bit 2 */ - new |= 0x4; + new &= (~0x20); /* Clear bit 5. */ + new |= 0x4; /* Set bit 2. */ pci_write_byte(dev, 0x45, new); @@ -311,16 +311,11 @@ static int enable_flash_sis5595(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_amd8111(struct pci_dev *dev, char *name) +static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* enable decoding at 0xffb00000 to 0xffffffff */ + /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, 0x43); new = old | 0xC0; if (new != old) { @@ -344,17 +339,10 @@ static int enable_flash_amd8111(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_ck804(struct pci_dev *dev, char *name) +static int enable_flash_ck804(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* dump_pci_device(dev); */ - old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { @@ -378,14 +366,14 @@ static int enable_flash_ck804(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_sb400(struct pci_dev *dev, char *name) +/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ +static int enable_flash_sb400(struct pci_dev *dev, const char *name) { uint8_t tmp; - struct pci_filter f; struct pci_dev *smbusdev; - /* then look for the smbus device */ + /* Look for the SMBus device. */ pci_filter_init((struct pci_access *)0, &f); f.vendor = 0x1002; f.device = 0x4372; @@ -397,21 +385,21 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name) } if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. aborting\n"); + fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); exit(1); } - /* enable some smbus stuff */ + /* Enable some SMBus stuff. */ tmp = pci_read_byte(smbusdev, 0x79); tmp |= 0x01; pci_write_byte(smbusdev, 0x79, tmp); - /* change southbridge */ + /* Change southbridge. */ tmp = pci_read_byte(dev, 0x48); tmp |= 0x21; pci_write_byte(dev, 0x48, tmp); - /* now become a bit silly. */ + /* Now become a bit silly. */ tmp = inb(0xc6f); outb(tmp, 0xeb); outb(tmp, 0xeb); @@ -423,19 +411,12 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_mcp55(struct pci_dev *dev, char *name) +static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ - unsigned char old, new, byte; - unsigned short word; - - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ + uint8_t old, new, byte; + uint16_t word; - /* dump_pci_device(dev); */ - - /* Set the 0-16 MB enable bits */ + /* Set the 0-16 MB enable bits. */ byte = pci_read_byte(dev, 0x88); byte |= 0xff; /* 256K */ pci_write_byte(dev, 0x88, byte); @@ -462,7 +443,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, char *name) return 0; } -static int enable_flash_ht1000(struct pci_dev *dev, char *name) +static int enable_flash_ht1000(struct pci_dev *dev, const char *name) { uint8_t byte; @@ -479,12 +460,12 @@ static int enable_flash_ht1000(struct pci_dev *dev, char *name) } typedef struct penable { - unsigned short vendor, device; - char *name; - int (*doit) (struct pci_dev * dev, char *name); + uint16_t vendor, device; + const char *name; + int (*doit) (struct pci_dev *dev, const char *name); } FLASH_ENABLE; -static FLASH_ENABLE enables[] = { +static const FLASH_ENABLE enables[] = { {0x1039, 0x0630, "SIS630", enable_flash_sis630}, {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4}, {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, @@ -517,17 +498,14 @@ static FLASH_ENABLE enables[] = { {0x1022, 0x2080, "AMD GEODE CS5536", enable_flash_cs5536}, {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, - /* this fallthrough looks broken. */ {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */ - {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804}, - - {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */ + {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI-S4 */ {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ @@ -535,19 +513,18 @@ static FLASH_ENABLE enables[] = { {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ - - {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ - + {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, }; int chipset_flash_enable(void) { struct pci_dev *dev = 0; - int ret = -2; /* nothing! */ + int ret = -2; /* Nothing! */ int i; - /* now let's try to find the chipset we have ... */ + /* Now let's try to find the chipset we have... */ + /* TODO: Use ARRAY_SIZE. */ for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) { dev = pci_dev_find(enables[i].vendor, enables[i].device); if (dev) -- cgit v1.2.3