From fbc38c71589910876466fd385a1f64f1c0c40eb7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 May 2021 10:50:40 +0200 Subject: chipset_enable.c: Add Gemini Lake eSPI PCI device ID Taken from coreboot `PCI_DEVICE_ID_INTEL_GLK_ESPI` macro, untested. Change-Id: Ie34527e56edcba4982f17b8e0aef0fc4280a52bc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/flashrom/+/54354 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Sam McNally --- chipset_enable.c | 1 + 1 file changed, 1 insertion(+) (limited to 'chipset_enable.c') diff --git a/chipset_enable.c b/chipset_enable.c index 025203cb5..cdd51aefe 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2084,6 +2084,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, -- cgit v1.2.3