From fa2cf255ec587f02baf987f21ab6d01de5db8c8e Mon Sep 17 00:00:00 2001 From: Sergii Dmytruk Date: Mon, 8 Nov 2021 00:05:12 +0200 Subject: dummyflasher: add SR2 and SR3 emulation harness Prepare everything for emulating SR2 and SR3 for chips that have it. This is needed for accessing SRP1 and WPS bits which are involved in write protection. The emulated register doesn't affect anything yet and will be tested by write-protection tests. TEST=check how input value affects status registers of emulated chip flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 | grep 'Initial status register' Mind that at this point there are no chips that emulate more than one status register. Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072 Tested-by: build bot (Jenkins) Reviewed-by: Anastasia Klimchuk Reviewed-by: Thomas Heijligen --- flashrom.8.tmpl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'flashrom.8.tmpl') diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 84e0fba32..0f7bc9748 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -816,7 +816,10 @@ You can specify the initial content of the chip's status register with the .sp syntax where .B content -is an 8-bit hexadecimal value. +is a hexadecimal value of up to 24 bits. For example, 0x332211 assigns 0x11 to +SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with +zeroes on the left. See datasheet for chosen chip for details about the +registers content. .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -- cgit v1.2.3