From 15f539c8c978e002f2b6397a7a74e1af817d5cb3 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 26 Aug 2010 21:27:17 -0700 Subject: ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE This aligns the upstream master branch with chromium's. On-the-fly opcode reprogramming is supported by both branches so the default opcode shouldn't matter. Review URL: http://codereview.chromium.org/3239001 Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64 Signed-off-by: Mayur Panchal Reviewed-on: https://review.coreboot.org/c/flashrom/+/34689 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- ichspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ichspi.c') diff --git a/ichspi.c b/ichspi.c index 5a86c96fa..12ee126fb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -324,7 +324,7 @@ static OPCODES O_ST_M25P = { { {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data - {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector + {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register -- cgit v1.2.3