From 76f28a3fc29b96c1c8cc76cba1279f92d2edc86e Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 26 Oct 2022 13:46:14 +1100 Subject: tree/: Rename 'internal_delay()' to 'default_delay()' The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- ichspi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'ichspi.c') diff --git a/ichspi.c b/ichspi.c index a6587c6b7..43590d64e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -875,7 +875,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -951,7 +951,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS)); @@ -991,7 +991,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -1071,7 +1071,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc)); @@ -1319,7 +1319,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout_us) { - internal_delay(8); + default_delay(8); } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout_us) { -- cgit v1.2.3