From 5ec84b3c096c9ace0bf3650206a0a9412e977c64 Mon Sep 17 00:00:00 2001 From: Thomas Heijligen Date: Tue, 19 Mar 2019 17:00:03 +0100 Subject: chipset_enable: Add support for discrete Cannon Lake PCHs The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel(R) 300 Series and Intel(R) C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel(R) 300 Series Chipset Families Platform Controller Hub Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier Reviewed-by: Jeremy Soller --- programmer.h | 1 + 1 file changed, 1 insertion(+) (limited to 'programmer.h') diff --git a/programmer.h b/programmer.h index dfa6ebd01..34ef33d50 100644 --- a/programmer.h +++ b/programmer.h @@ -626,6 +626,7 @@ enum ich_chipset { CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, }; -- cgit v1.2.3