From f6d702e2d09f604830070fc0079374955481be5d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 28 May 2022 16:48:26 +0200 Subject: spi25_statusreg: Allow WRSR_EXT for Status Register 3 Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) Reviewed-by: Nikolai Artemiev Reviewed-by: Arthur Heymans Reviewed-by: Thomas Heijligen --- tests/chip_wp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/chip_wp.c b/tests/chip_wp.c index 8b209bd33..95e6b05ce 100644 --- a/tests/chip_wp.c +++ b/tests/chip_wp.c @@ -67,7 +67,7 @@ static const struct flashchip chip_W25Q128_V = { .read = spi_chip_read, .write = spi_chip_write_256, .unlock = spi_disable_blockprotect, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, .block_erasers = { { -- cgit v1.2.3