From 4095ed797f87c92b52e15d9f6fdc0b895c414cc9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 20 Aug 2014 15:39:32 +0000 Subject: Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Corresponding to flashrom svn r1844. Signed-off-by: Duncan Laurie Signed-off-by: Martin Roth Signed-off-by: Stefan Tauner Tested-by: Marc Jones Tested-by: Stefan Tauner Tested-by: Thomas Reardon Tested-by: Wen Wang Acked-by: Marc Jones Acked-by: Stefan Tauner --- util/ich_descriptors_tool/ich_descriptors_tool.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'util') diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index e77593e11..78cb15b09 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -118,6 +118,7 @@ static void usage(char *argv[], char *error) "\t- \"ich8\",\n" "\t- \"ich9\",\n" "\t- \"ich10\",\n" +"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -202,6 +203,8 @@ int main(int argc, char *argv[]) else if ((strcmp(csn, "8") == 0) || (strcmp(csn, "lynx") == 0)) cs = CHIPSET_8_SERIES_LYNX_POINT; + else if ((strcmp(csn, "silvermont") == 0)) + cs = CHIPSET_BAYTRAIL; } ret = read_ich_descriptors_from_dump(buf, len, &desc); -- cgit v1.2.3