1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2009,2010 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <sys/types.h>
#if !defined (__DJGPP__)
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#endif
#include "flash.h"
#if defined(__i386__) || defined(__x86_64__)
/* sync primitive is not needed because x86 uses uncached accesses
* which have a strongly ordered memory model.
*/
static inline void sync_primitive(void)
{
}
#if defined(__FreeBSD__) || defined(__DragonFly__)
int io_fd;
#endif
void get_io_perms(void)
{
#if defined(__DJGPP__)
/* We have full permissions by default. */
return;
#else
#if defined (__sun) && (defined(__i386) || defined(__amd64))
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif defined(__FreeBSD__) || defined (__DragonFly__)
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
#else
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
"You need to be root.\n", strerror(errno));
exit(1);
}
#endif
}
void release_io_perms(void)
{
#if defined(__FreeBSD__) || defined(__DragonFly__)
close(io_fd);
#endif
}
#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
static inline void sync_primitive(void)
{
/* Prevent reordering and/or merging of reads/writes to hardware.
* Such reordering and/or merging would break device accesses which
* depend on the exact access order.
*/
asm("eieio" : : : "memory");
}
/* PCI port I/O is not yet implemented on PowerPC. */
void get_io_perms(void)
{
}
/* PCI port I/O is not yet implemented on PowerPC. */
void release_io_perms(void)
{
}
#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
* in mode 2 which has a strongly ordered memory model.
*/
static inline void sync_primitive(void)
{
}
/* PCI port I/O is not yet implemented on MIPS. */
void get_io_perms(void)
{
}
/* PCI port I/O is not yet implemented on MIPS. */
void release_io_perms(void)
{
}
#else
#error Unknown architecture
#endif
void mmio_writeb(uint8_t val, void *addr)
{
*(volatile uint8_t *) addr = val;
sync_primitive();
}
void mmio_writew(uint16_t val, void *addr)
{
*(volatile uint16_t *) addr = val;
sync_primitive();
}
void mmio_writel(uint32_t val, void *addr)
{
*(volatile uint32_t *) addr = val;
sync_primitive();
}
uint8_t mmio_readb(void *addr)
{
return *(volatile uint8_t *) addr;
}
uint16_t mmio_readw(void *addr)
{
return *(volatile uint16_t *) addr;
}
uint32_t mmio_readl(void *addr)
{
return *(volatile uint32_t *) addr;
}
void mmio_le_writeb(uint8_t val, void *addr)
{
mmio_writeb(cpu_to_le8(val), addr);
}
void mmio_le_writew(uint16_t val, void *addr)
{
mmio_writew(cpu_to_le16(val), addr);
}
void mmio_le_writel(uint32_t val, void *addr)
{
mmio_writel(cpu_to_le32(val), addr);
}
uint8_t mmio_le_readb(void *addr)
{
return le_to_cpu8(mmio_readb(addr));
}
uint16_t mmio_le_readw(void *addr)
{
return le_to_cpu16(mmio_readw(addr));
}
uint32_t mmio_le_readl(void *addr)
{
return le_to_cpu32(mmio_readl(addr));
}
|