blob: 0073c7125edd8fa285ceea55fca2f3965e215ca5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
|
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SPI_H__
#define __SPI_H__ 1
/*
* Contains the generic SPI headers
*/
#define JEDEC_MAX_ADDR_LEN 0x04
/* Read Electronic ID */
#define JEDEC_RDID 0x9f
#define JEDEC_RDID_OUTSIZE 0x01
/* INSIZE may be 0x04 for some chips*/
#define JEDEC_RDID_INSIZE 0x03
/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
#define AT25F_RDID_OUTSIZE 0x01
#define AT25F_RDID_INSIZE 0x02
/* Read Electronic Manufacturer Signature */
#define JEDEC_REMS 0x90
#define JEDEC_REMS_OUTSIZE 0x04
#define JEDEC_REMS_INSIZE 0x02
/* Read Serial Flash Discoverable Parameters (SFDP) */
#define JEDEC_SFDP 0x5a
#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
/* JEDEC_SFDP_INSIZE : any length */
/* Read Electronic Signature */
#define JEDEC_RES 0xab
#define JEDEC_RES_OUTSIZE 0x04
/* INSIZE may be 0x02 for some chips*/
#define JEDEC_RES_INSIZE 0x01
/* Write Enable */
#define JEDEC_WREN 0x06
#define JEDEC_WREN_OUTSIZE 0x01
#define JEDEC_WREN_INSIZE 0x00
/* Write Disable */
#define JEDEC_WRDI 0x04
#define JEDEC_WRDI_OUTSIZE 0x01
#define JEDEC_WRDI_INSIZE 0x00
/* Chip Erase 0x60 is supported by Macronix/SST chips. */
#define JEDEC_CE_60 0x60
#define JEDEC_CE_60_OUTSIZE 0x01
#define JEDEC_CE_60_INSIZE 0x00
/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
#define JEDEC_CE_62 0x62
#define JEDEC_CE_62_OUTSIZE 0x01
#define JEDEC_CE_62_INSIZE 0x00
/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
#define JEDEC_CE_C7 0xc7
#define JEDEC_CE_C7_OUTSIZE 0x01
#define JEDEC_CE_C7_INSIZE 0x00
/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
#define JEDEC_BE_50 0x50
#define JEDEC_BE_50_OUTSIZE 0x04
#define JEDEC_BE_50_INSIZE 0x00
/* Block Erase 0x52 is supported by SST and old Atmel chips. */
#define JEDEC_BE_52 0x52
#define JEDEC_BE_52_OUTSIZE 0x04
#define JEDEC_BE_52_INSIZE 0x00
/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
#define JEDEC_BE_81 0x81
#define JEDEC_BE_81_OUTSIZE 0x04
#define JEDEC_BE_81_INSIZE 0x00
/* Block Erase 0xc4 is supported by Micron chips. */
#define JEDEC_BE_C4 0xc4
#define JEDEC_BE_C4_OUTSIZE 0x04
#define JEDEC_BE_C4_INSIZE 0x00
/* Block Erase 0xd8 is supported by EON/Macronix chips. */
#define JEDEC_BE_D8 0xd8
#define JEDEC_BE_D8_OUTSIZE 0x04
#define JEDEC_BE_D8_INSIZE 0x00
/* Block Erase 0xd7 is supported by PMC chips. */
#define JEDEC_BE_D7 0xd7
#define JEDEC_BE_D7_OUTSIZE 0x04
#define JEDEC_BE_D7_INSIZE 0x00
/* Sector Erase 0x20 is supported by Macronix/SST chips. */
#define JEDEC_SE 0x20
#define JEDEC_SE_OUTSIZE 0x04
#define JEDEC_SE_INSIZE 0x00
/* Page Erase 0xDB */
#define JEDEC_PE 0xDB
#define JEDEC_PE_OUTSIZE 0x04
#define JEDEC_PE_INSIZE 0x00
/* Read Status Register */
#define JEDEC_RDSR 0x05
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
#define SPI_SR_AAI (0x01 << 6)
/* Write Status Enable */
#define JEDEC_EWSR 0x50
#define JEDEC_EWSR_OUTSIZE 0x01
#define JEDEC_EWSR_INSIZE 0x00
/* Write Status Register */
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
/* Exit 4-byte Address Mode */
#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9
/* Write Extended Address Register */
#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
/* Read Extended Address Register */
#define JEDEC_READ_EXT_ADDR_REG 0xC8
/* Read the memory */
#define JEDEC_READ 0x03
#define JEDEC_READ_OUTSIZE 0x04
/* JEDEC_READ_INSIZE : any length */
/* Read the memory (with delay after sending address) */
#define JEDEC_READ_FAST 0x0b
/* Write memory byte */
#define JEDEC_BYTE_PROGRAM 0x02
#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
/* Write AAI word (SST25VF080B) */
#define JEDEC_AAI_WORD_PROGRAM 0xad
#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
/* Read the memory with 4-byte address
From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
#define JEDEC_READ_4BA 0x13
/* Read the memory with 4-byte address (and delay after sending address)
From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
#define JEDEC_READ_4BA_FAST 0x0c
/* Write memory byte with 4-byte address
From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
#define JEDEC_BYTE_PROGRAM_4BA 0x12
/* Error codes */
#define SPI_GENERIC_ERROR -1
#define SPI_INVALID_OPCODE -2
#define SPI_INVALID_ADDRESS -3
#define SPI_INVALID_LENGTH -4
#define SPI_FLASHROM_BUG -5
#define SPI_PROGRAMMER_ERROR -6
#endif /* !__SPI_H__ */
|
