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authorDmitry Osipenko <digetx@gmail.com>2021-03-02 15:24:58 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-11-26 11:40:42 +0100
commit4a1502dafbaccbc49689609a78f489bfd26b8916 (patch)
treed10dce92dd70e70f0e7ddd9bfabc29b0ee866d90
parent4460257207166807a333257852aa5ba2a1f668fa (diff)
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soc/tegra: pmc: Fix imbalanced clock disabling in error code path
commit 19221e3083020bd9537624caa0ee0145ed92ba36 upstream. The tegra_powergate_power_up() has a typo in the error code path where it will try to disable clocks twice, fix it. In practice that error never happens, so this is a minor correction. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/soc/tegra/pmc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 71f4ff3e13b4..3574021a0a36 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -395,7 +395,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
err = tegra_powergate_enable_clocks(pg);
if (err)
- goto disable_clks;
+ goto powergate_off;
usleep_range(10, 20);