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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-07-17 18:07:31 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-07-17 18:07:31 -0700 |
| commit | 0ffb8a4c96e55ecf0e572aec1a0220af3da84e22 (patch) | |
| tree | ea497c6728d2b93b31f1f4535a1413a436a59683 | |
| parent | 5b9ac6c2a735f5b1721e0bc7331f8707190f9ef6 (diff) | |
| parent | 76be2f9823b10c07daf814cb6c732eb1456a0b9e (diff) | |
| download | linux-stable-0ffb8a4c96e55ecf0e572aec1a0220af3da84e22.tar.gz linux-stable-0ffb8a4c96e55ecf0e572aec1a0220af3da84e22.tar.bz2 linux-stable-0ffb8a4c96e55ecf0e572aec1a0220af3da84e22.zip | |
Merge tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT Bindings:
- Convert and add a bunch of IBM FSI related bindings
- Add a new schema listing legacy compatibles which will (probably)
never be documented. This will silence various checks warning about
them.
- Add bindings for Sierra Wireless mangOH Green SPI IoT interface,
new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75
GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and
CSI-2 blocks
- Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema
- Drop obsolete stericsson,abx500.txt
DT core:
- Update dtc to upstream version v1.7.0-93-g1df7b047fe43
- Add support to run DT validation on DTs with applied overlays
- Add helper for creating boolean properties in dynamic nodes and use
that for dynamic PCI nodes
- Clean-up early parsing of '#{address,size}-cells'"
* tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
dt-bindings: timer: sprd-timer: convert to YAML
dt-bindings: incomplete-devices: document devices without bindings
dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface
scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43
dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node
dt-bindings: soc: fsl: cpm_qe: convert to yaml format
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml
dt-bindings: soc: fsl: Convert q(b)man-* to yaml format
dt-bindings: misc: fsl,qoriq-mc: convert to yaml format
dt-bindings: drop stale Anson Huang from maintainers
...
97 files changed, 2751 insertions, 1301 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index cc5a21b47e26..f308ff6c3532 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -147,6 +147,7 @@ properties: - arm,cortex-a710 - arm,cortex-a715 - arm,cortex-a720 + - arm,cortex-a725 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -161,10 +162,15 @@ properties: - arm,cortex-x2 - arm,cortex-x3 - arm,cortex-x4 + - arm,cortex-x925 - arm,neoverse-e1 - arm,neoverse-n1 - arm,neoverse-n2 + - arm,neoverse-n3 - arm,neoverse-v1 + - arm,neoverse-v2 + - arm,neoverse-v3 + - arm,neoverse-v3ae - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml index 526f508cb98d..bd39cf107f3e 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX7ULP System Integration Module maintainers: - - Anson Huang <anson.huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | The system integration module (SIM) provides system control and chip configuration diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml index bae4fcb3aacc..cd3c04c883df 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 Quad Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml index c85ff6ea3d24..6713bbb14f30 100644 --- a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SoloLite Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml index 6b549ed1493c..6d64cf9463c9 100644 --- a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SLL Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml index 55dcad18b7c6..77afa4b81cf7 100644 --- a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SoloX Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml index be54d4df5afa..d57e18a210cc 100644 --- a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 UltraLite Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml index e7d8427e4957..880d602d09f4 100644 --- a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml @@ -8,7 +8,6 @@ title: Freescale i.MX7 Dual Clock Controller maintainers: - Frank Li <Frank.Li@nxp.com> - - Anson Huang <Anson.Huang@nxp.com> description: | The clock consumer should specify the desired clock by having the clock diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index 80539f88bc27..c643d4a81478 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8M Family Clock Control Module maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> description: | NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt deleted file mode 100644 index dbaa886b223e..000000000000 --- a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt +++ /dev/null @@ -1,20 +0,0 @@ -Clock bindings for ST-Ericsson ABx500 clocks - -Required properties : -- compatible : shall contain the following: - "stericsson,ab8500-clk" -- #clock-cells should be <1> - -The ABx500 clocks need to be placed as a subnode of an AB8500 -device node, see mfd/ab8500.txt - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/ste-ab8500.h header and can be used in device -tree sources. - -Example: - -clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 1e08648f5bc7..bbaaa783d184 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -21,7 +21,9 @@ properties: items: - const: lg,sw43408 - reg: true + reg: + maxItems: 1 + port: true vddi-supply: true vpnl-supply: true diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml index b17765b2b351..ec445ff5631c 100644 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml @@ -28,6 +28,9 @@ properties: to work with the indicated panel. The raydium,rm69380 compatible shall always be provided as a fallback. + reg: + maxItems: 1 + avdd-supply: description: Analog voltage rail @@ -38,8 +41,6 @@ properties: maxItems: 1 description: phandle of gpio for reset line - This should be active low - reg: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index deb64cb9ca3e..4df4e61895d2 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -27,6 +27,7 @@ properties: - qcom,qcm2290-gpi-dma - qcom,qdu1000-gpi-dma - qcom,sc7280-gpi-dma + - qcom,sdx75-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma diff --git a/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml new file mode 100644 index 000000000000..dfcc2fafa68d --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed FSI master + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The AST2600 and later contain two identical FSI masters. They share a + clock and have a separate interrupt line and output pins. + +properties: + compatible: + enum: + - aspeed,ast2600-fsi-master + - aspeed,ast2700-fsi-master + + clocks: + maxItems: 1 + + cfam-reset-gpios: + maxItems: 1 + description: + Output GPIO pin for CFAM reset + + fsi-routing-gpios: + maxItems: 1 + description: + Output GPIO pin for setting the FSI mux (internal or cabled) + + fsi-mux-gpios: + maxItems: 1 + description: + Input GPIO pin for detecting the desired FSI mux state + + interrupts: + maxItems: 1 + +if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-fsi-master +then: + properties: + reg: + maxItems: 1 +else: + properties: + reg: + minItems: 1 + items: + - description: OPB control registers + - description: FSI controller registers + - description: FSI link address space + reg-names: + items: + - const: opb + - const: ctrl + - const: fsi + +required: + - compatible + - reg + - clocks + - interrupts + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + #include <dt-bindings/gpio/aspeed-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + fsi-master@1e79b000 { + compatible = "aspeed,ast2600-fsi-master"; + reg = <0x1e79b000 0x94>; + #address-cells = <2>; + #size-cells = <0>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + }; + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + fsi-master@21800000 { + compatible = "aspeed,ast2700-fsi-master"; + reg = <0x0 0x21800000 0x0 0x100>, + <0x0 0x21000000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x1000000>; + reg-names = "opb", "ctrl", "fsi"; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&intc 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi0_default>; + clocks = <&syscon 40>; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/fsi-controller.yaml b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml new file mode 100644 index 000000000000..ffe191921b26 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSI Controller Common Properties + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The + FSI bus is connected to a CFAM (Common FRU Access Macro) which contains + various engines such as I2C controllers, SPI controllers, etc. + +properties: + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + '#interrupt-cells': + const: 1 + + bus-frequency: + minimum: 1 + maximum: 200000000 + + interrupt-controller: true + + no-scan-on-init: + $ref: /schemas/types.yaml#/definitions/flag + description: + The FSI controller cannot scan the bus during initialization. + +patternProperties: + "cfam@[0-9a-f],[0-9a-f]": + type: object + properties: + chip-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Processor index, a global unique chip ID which is used to identify + the physical location of the chip in a system specific way. + + bus-frequency: + minimum: 1 + maximum: 100000000 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + required: + - reg + + additionalProperties: true + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt b/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt deleted file mode 100644 index 9853fefff5d8..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device-tree bindings for AST2600 FSI master -------------------------------------------- - -The AST2600 contains two identical FSI masters. They share a clock and have a -separate interrupt line and output pins. - -Required properties: - - compatible: "aspeed,ast2600-fsi-master" - - reg: base address and length - - clocks: phandle and clock number - - interrupts: platform dependent interrupt description - - pinctrl-0: phandle to pinctrl node - - pinctrl-names: pinctrl state - -Optional properties: - - cfam-reset-gpios: GPIO for CFAM reset - - - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled) - - fsi-mux-gpios: GPIO for detecting the desired FSI mux state - - -Examples: - - fsi-master { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b000 0x94>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi1_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - - fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; - fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml b/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml index e2ca0b000471..ad5c83f48425 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml +++ b/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml @@ -9,11 +9,10 @@ title: IBM FSI-attached SPI controllers maintainers: - Eddie James <eajames@linux.ibm.com> -description: | +description: This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this - node will always be a child of an FSI CFAM node; see fsi.txt for details on - FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of - SPI controllers. + node will always be a child of an FSI CFAM node. This FSI2SPI engine provides + access to a number of SPI controllers. properties: compatible: @@ -24,6 +23,17 @@ properties: items: - description: FSI slave address + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^spi@[0-9a-f]+$": + type: object + $ref: /schemas/spi/ibm,spi-fsi.yaml + required: - compatible - reg @@ -35,4 +45,22 @@ examples: fsi2spi@1c00 { compatible = "ibm,fsi2spi"; reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <1000000>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml index 442cecdc57cb..e49ace3ca339 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml +++ b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml @@ -26,7 +26,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml new file mode 100644 index 000000000000..29ea80ff915e --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached FSI Hub Controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The FSI Hub Controller is an FSI controller, providing a number of FSI links, + located on a CFAM. Therefore this node will always be a child of an FSI CFAM + node. + +properties: + compatible: + enum: + - ibm,p9-fsi-controller + + reg: + items: + - description: FSI slave address + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt deleted file mode 100644 index e73358075a90..000000000000 --- a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt +++ /dev/null @@ -1,16 +0,0 @@ -Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC) ------------------------------------------------------------------------------ - -This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from -a service processor. See fsi.txt for details on bindings for FSI slave and CFAM -nodes. The OCC is not an FSI slave device itself, rather it is accessed -through the SBE FIFO. - -Required properties: - - compatible = "ibm,p9-occ" or "ibm,p10-occ" - -Examples: - - occ { - compatible = "ibm,p9-occ"; - }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml new file mode 100644 index 000000000000..537eac70447c --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-occ.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached On-Chip Controller (OCC) + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The POWER processor On-Chip Controller (OCC) helps manage power and + thermals for the system, accessed through the FSI-attached SBEFIFO + from a service processor. + +properties: + compatible: + enum: + - ibm,p9-occ + - ibm,p10-occ + + hwmon: + type: object + $ref: /schemas/hwmon/ibm,occ-hwmon.yaml + +required: + - compatible + +additionalProperties: false + +examples: + - | + occ { + compatible = "ibm,p9-occ"; + + hwmon { + compatible = "ibm,p9-occ-hwmon"; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml new file mode 100644 index 000000000000..3cd966fb3c0d --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-sbefifo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SBEFIFO engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The SBEFIFO is an FSI CFAM engine that provides an interface to the + POWER processor Self Boot Engine (SBE). This node will always be a child + of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-sbefifo + - ibm,odyssey-sbefifo + + reg: + items: + - description: FSI slave address + + occ: + type: object + $ref: ibm,p9-occ.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fsi-slave-engine@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p9-occ"; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml new file mode 100644 index 000000000000..8cd14a70bedf --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-scom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SCOM engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The SCOM engine is an interface to the POWER processor PIB (Pervasive + Interconnect Bus). This node will always be a child of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-scom + - ibm,i2cr-scom + + reg: + items: + - description: FSI slave address + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml index 918776d16ef3..e1fc8bb6d379 100644 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX/MXC GPIO controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index dfa1133f8c5e..8ff54369d16c 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -8,7 +8,6 @@ title: Freescale MXS GPIO controller maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <Anson.Huang@nxp.com> description: | The Freescale MXS GPIO controller is part of MXS PIN controller. diff --git a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt b/Documentation/devicetree/bindings/i2c/i2c-fsi.txt deleted file mode 100644 index b1be2ceb7e69..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt +++ /dev/null @@ -1,40 +0,0 @@ -Device-tree bindings for FSI-attached I2C master and busses ------------------------------------------------------------ - -Required properties: - - compatible = "ibm,i2c-fsi"; - - reg = < address size >; : The FSI CFAM address and address - space size. - - #address-cells = <1>; : Number of address cells in child - nodes. - - #size-cells = <0>; : Number of size cells in child nodes. - - child nodes : Nodes to describe busses off the I2C - master. - -Child node required properties: - - reg = < port number > : The port number on the I2C master. - -Child node optional properties: - - child nodes : Nodes to describe devices on the I2C - bus. - -Examples: - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = < 0x1800 0x400 >; - #address-cells = <1>; - #size-cells = <0>; - - i2c-bus@0 { - reg = <0>; - }; - - i2c-bus@1 { - reg = <1>; - - eeprom@50 { - compatible = "vendor,dev-name"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml index 54d500be6aaa..1dcb9c78de3b 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Low Power Inter IC (LPI2C) for i.MX maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml b/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml new file mode 100644 index 000000000000..40ea82942e4d --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ibm,i2c-fsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached I2C controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + This I2C controller is an FSI CFAM engine, providing access to a number of + I2C busses. Therefore this node will always be a child of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,i2c-fsi + + reg: + items: + - description: FSI slave address + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^i2c-bus@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + + allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + unevaluatedProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml b/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml index 6b54d32323fc..fbe8c2eb0857 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml +++ b/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MAG3110 magnetometer sensor maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Jonathan Cameron <jic23@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/incomplete-devices.yaml b/Documentation/devicetree/bindings/incomplete-devices.yaml new file mode 100644 index 000000000000..cfc1d39441b1 --- /dev/null +++ b/Documentation/devicetree/bindings/incomplete-devices.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/incomplete-devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rejected, Legacy or Incomplete Devices + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + Some devices will not or should not get a proper Devicetree bindings, but + their compatibles are present in Linux drivers for various reasons. + + Examples are devices using ACPI PRP0001 with non-updatable firmware/ACPI + tables or old PowerPC platforms without in-tree DTS. + + Following list of devices is an incomplete schema with a goal to pass DT schema + checks on undocumented compatibles but also reject any DTS file using such + un-approved compatible. + + Usage of any of following compatibles is not allowed in Devicetree sources, + even if they come from immutable firmware. + +properties: + compatible: + oneOf: + - description: + Rejected compatibles in Devicetree, but used in ACPI-based devices + with non-updatable firmware/ACPI tables (via ACPI PRP0001) + enum: + - broadcom,bcm5241 + - ltr,ltrf216a + + - description: Legacy compatibles used on Macintosh devices + enum: + - adm1030 + - bmac+ + - heathrow-media-bay + - keylargo-media-bay + - lm87cimt + - MAC,adm1030 + - MAC,ds1775 + - max6690 + - ohare-media-bay + - ohare-swim3 + - smu-sat + - swim3 + + - description: Legacy compatibles used on other PowerPC devices + enum: + - 1682m-rng + - IBM,lhca + - IBM,lhea + - IBM,lhea-ethernet + - mpc5200b-fec-phy + - mpc5200-serial + - mpc5200-sram + - ohci-be + - ohci-bigendian + - ohci-le + + - description: Legacy compatibles used on SPARC devices + enum: + - bq4802 + - ds1287 + - isa-m5819p + - isa-m5823p + - m5819 + - sab82532 + - SUNW,bbc-beep + - SUNW,bbc-i2c + - SUNW,CS4231 + - SUNW,ebus-pic16f747-env + - SUNW,kt-cwq + - SUNW,kt-mau + - SUNW,n2-cwq + - SUNW,n2-mau + - SUNW,niusl + - SUNW,smbus-beep + - SUNW,sun4v-console + - SUNW,sun4v-pci + - SUNW,vf-cwq + - SUNW,vf-mau + + - description: Incomplete and/or legacy compatibles for unknown devices + enum: + - electra-cf + - i2cpcf,8584 + - virtio,uml + + - description: Linux kernel unit tests and sample code + enum: + - audio-graph-card2-custom-sample + - compat1 + - compat2 + - compat3 + - linux,spi-loopback-test + - mailbox-test + - regulator-virtual-consumer + + - description: + Devices on MIPS platform, without any DTS users. These are + unlikely to get converted to DT schema. + enum: + - mti,ranchu + + - description: + Devices on PowerPC platform, without any DTS users. These are + unlikely to get converted to DT schema. + enum: + - fujitsu,coral + - fujitsu,lime + - fujitsu,MB86276 + - fujitsu,MB86277 + - fujitsu,MB86293 + - fujitsu,MB86294 + - fujitsu,mint + - ibm,axon-msic + - ibm,pmemory + - ibm,pmemory-v2 + - ibm,power-rng + - ibm,ppc4xx-spi + - ibm,sdram-4xx-ddr2 + - ibm,secureboot + - ibm,secureboot-v1 + - ibm,secureboot-v2 + - ibm,secvar-backend + - sgy,gpio-halt + - wrs,epld-localbus + +required: + - compatible + - broken-usage-of-incorrect-compatible + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml index 20ad4ad82ad6..aae676ba30ed 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml @@ -14,7 +14,10 @@ properties: oneOf: - const: fsl,imx-irqsteer - items: - - const: fsl,imx8m-irqsteer + - enum: + - fsl,imx8m-irqsteer + - fsl,imx8mp-irqsteer + - fsl,imx8qxp-irqsteer - const: fsl,imx-irqsteer reg: @@ -42,6 +45,9 @@ properties: clock-names: const: ipg + power-domains: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": @@ -70,6 +76,21 @@ required: - fsl,channel - fsl,num-irqs +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-irqsteer + - fsl,imx8qxp-irqsteer + then: + required: + - power-domains + else: + properties: + power-domains: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml new file mode 100644 index 000000000000..9ba8d4d73351 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape SCFG PCIe MSI controller + +description: | + This interrupt controller hardware is a second level interrupt controller that + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based + platforms. If interrupt-parent is not provided, the default parent interrupt + controller will be used. + + Each PCIe node needs to have property msi-parent that points to + MSI controller node + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + enum: + - fsl,ls1012a-msi + - fsl,ls1021a-msi + - fsl,ls1043a-msi + - fsl,ls1043a-v1.1-msi + - fsl,ls1046a-msi + + reg: + maxItems: 1 + + '#msi-cells': + const: 1 + + interrupts: + items: + - description: Shared MSI interrupt group 0 + - description: Shared MSI interrupt group 1 + - description: Shared MSI interrupt group 2 + - description: Shared MSI interrupt group 3 + minItems: 1 + +required: + - compatible + - reg + - msi-controller + - interrupts + +allOf: + - $ref: msi-controller.yaml + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1046a-msi + then: + properties: + interrupts: + minItems: 4 + else: + properties: + interrupts: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@1571000 { + compatible = "fsl,ls1043a-msi"; + reg = <0x1571000 0x8>; + msi-controller; + #msi-cells = <1>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt deleted file mode 100644 index 454ce04d6787..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale Layerscape SCFG PCIe MSI controller - -Required properties: - -- compatible: should be "fsl,<soc-name>-msi" to identify - Layerscape PCIe MSI controller block such as: - "fsl,ls1021a-msi" - "fsl,ls1043a-msi" - "fsl,ls1046a-msi" - "fsl,ls1043a-v1.1-msi" - "fsl,ls1012a-msi" -- msi-controller: indicates that this is a PCIe MSI controller node -- reg: physical base address of the controller and length of memory mapped. -- interrupts: an interrupt to the parent interrupt controller. - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. If interrupt-parent is not provided, the default parent interrupt -controller will be used. -Each PCIe node needs to have property msi-parent that points to -MSI controller node - -Examples: - - msi1: msi-controller@1571000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>, - msi-controller; - interrupts = <0 116 0x4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 4bdc8321904b..985fa10abb99 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,6 +30,7 @@ properties: - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc + - qcom,sc8180x-pdc - qcom,sc8280xp-pdc - qcom,sdm670-pdc - qcom,sdm845-pdc diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml index 1e72b8808d24..bc1245127025 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -19,6 +19,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-cru # RZ/G2UL - renesas,r9a07g044-cru # RZ/G2{L,LC} - renesas,r9a07g054-cru # RZ/V2L - const: renesas,rzg2l-cru @@ -87,10 +88,6 @@ properties: Input port node, describing the Image Processing module connected to the CSI-2 receiver. - required: - - port@0 - - port@1 - required: - compatible - reg @@ -102,6 +99,36 @@ required: - reset-names - power-domains +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g044-cru + - renesas,r9a07g054-cru + then: + properties: + ports: + required: + - port@0 + - port@1 + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-cru + then: + properties: + ports: + properties: + port@0: false + + required: + - port@1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml index 67eea2ac1d22..7faa12fecd5b 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml @@ -19,6 +19,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-csi2 # RZ/G2UL - renesas,r9a07g044-csi2 # RZ/G2{L,LC} - renesas,r9a07g054-csi2 # RZ/V2L - const: renesas,rzg2l-csi2 diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml index 71547eee9919..5447f1dddedf 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Multi Mode DDR controller (MMDC) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt deleted file mode 100644 index 7b486d4985dc..000000000000 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt +++ /dev/null @@ -1,196 +0,0 @@ -* Freescale Management Complex - -The Freescale Management Complex (fsl-mc) is a hardware resource -manager that manages specialized hardware objects used in -network-oriented packet processing applications. After the fsl-mc -block is enabled, pools of hardware resources are available, such as -queues, buffer pools, I/O interfaces. These resources are building -blocks that can be used to create functional hardware objects/devices -such as network interfaces, crypto accelerator instances, L2 switches, -etc. - -For an overview of the DPAA2 architecture and fsl-mc bus see: -Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst - -As described in the above overview, all DPAA2 objects in a DPRC share the -same hardware "isolation context" and a 10-bit value called an ICID -(isolation context id) is expressed by the hardware to identify -the requester. - -The generic 'iommus' property is insufficient to describe the relationship -between ICIDs and IOMMUs, so an iommu-map property is used to define -the set of possible ICIDs under a root DPRC and how they map to -an IOMMU. - -For generic IOMMU bindings, see -Documentation/devicetree/bindings/iommu/iommu.txt. - -For arm-smmu binding, see: -Documentation/devicetree/bindings/iommu/arm,smmu.yaml. - -The MSI writes are accompanied by sideband data which is derived from the ICID. -The msi-map property is used to associate the devices with both the ITS -controller and the sideband data which accompanies the writes. - -For generic MSI bindings, see -Documentation/devicetree/bindings/interrupt-controller/msi.txt. - -For GICv3 and GIC ITS bindings, see: -Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. - -Required properties: - - - compatible - Value type: <string> - Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex - compatible with this binding must have Block Revision - Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in - the MC control register region. - - - reg - Value type: <prop-encoded-array> - Definition: A standard property. Specifies one or two regions - defining the MC's registers: - - -the first region is the command portal for the - this machine and must always be present - - -the second region is the MC control registers. This - region may not be present in some scenarios, such - as in the device tree presented to a virtual machine. - - - ranges - Value type: <prop-encoded-array> - Definition: A standard property. Defines the mapping between the child - MC address space and the parent system address space. - - The MC address space is defined by 3 components: - <region type> <offset hi> <offset lo> - - Valid values for region type are - 0x0 - MC portals - 0x1 - QBMAN portals - - - #address-cells - Value type: <u32> - Definition: Must be 3. (see definition in 'ranges' property) - - - #size-cells - Value type: <u32> - Definition: Must be 1. - -Sub-nodes: - - The fsl-mc node may optionally have dpmac sub-nodes that describe - the relationship between the Ethernet MACs which belong to the MC - and the Ethernet PHYs on the system board. - - The dpmac nodes must be under a node named "dpmacs" which contains - the following properties: - - - #address-cells - Value type: <u32> - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 1. - - - #size-cells - Value type: <u32> - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 0. - - These nodes must have the following properties: - - - compatible - Value type: <string> - Definition: Must be "fsl,qoriq-mc-dpmac". - - - reg - Value type: <prop-encoded-array> - Definition: Specifies the id of the dpmac. - - - phy-handle - Value type: <phandle> - Definition: Specifies the phandle to the PHY device node associated - with the this dpmac. -Optional properties: - -- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier - data. - - The property is an arbitrary number of tuples of - (icid-base,iommu,iommu-base,length). - - Any ICID i in the interval [icid-base, icid-base + length) is - associated with the listed IOMMU, with the iommu-specifier - (i - icid-base + iommu-base). - -- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier - data. - - The property is an arbitrary number of tuples of - (icid-base,gic-its,msi-base,length). - - Any ICID in the interval [icid-base, icid-base + length) is - associated with the listed GIC ITS, with the msi-specifier - (i - icid-base + msi-base). - -Deprecated properties: - - - msi-parent - Value type: <phandle> - Definition: Describes the MSI controller node handling message - interrupts for the MC. When there is no translation - between the ICID and deviceID this property can be used - to describe the MSI controller used by the devices on the - mc-bus. - The use of this property for mc-bus is deprecated. Please - use msi-map. - -Example: - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - ... - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - ... - } - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - ... - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - /* define map for ICIDs 23-64 */ - iommu-map = <23 &smmu 23 41>; - /* define msi map for ICIDs 23-64 */ - msi-map = <23 &its 23 41>; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - phy-handle = <&mdio0_phy0>; - } - } - }; diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml new file mode 100644 index 000000000000..01b00d89a992 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Management Complex + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + The Freescale Management Complex (fsl-mc) is a hardware resource + manager that manages specialized hardware objects used in + network-oriented packet processing applications. After the fsl-mc + block is enabled, pools of hardware resources are available, such as + queues, buffer pools, I/O interfaces. These resources are building + blocks that can be used to create functional hardware objects/devices + such as network interfaces, crypto accelerator instances, L2 switches, + etc. + + For an overview of the DPAA2 architecture and fsl-mc bus see: + Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst + + As described in the above overview, all DPAA2 objects in a DPRC share the + same hardware "isolation context" and a 10-bit value called an ICID + (isolation context id) is expressed by the hardware to identify + the requester. + + The generic 'iommus' property is insufficient to describe the relationship + between ICIDs and IOMMUs, so an iommu-map property is used to define + the set of possible ICIDs under a root DPRC and how they map to + an IOMMU. + + For generic IOMMU bindings, see + Documentation/devicetree/bindings/iommu/iommu.txt. + + For arm-smmu binding, see: + Documentation/devicetree/bindings/iommu/arm,smmu.yaml. + + The MSI writes are accompanied by sideband data which is derived from the ICID. + The msi-map property is used to associate the devices with both the ITS + controller and the sideband data which accompanies the writes. + + For generic MSI bindings, see + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + + For GICv3 and GIC ITS bindings, see: + Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. + +properties: + compatible: + enum: + - fsl,qoriq-mc + description: + Must be "fsl,qoriq-mc". A Freescale Management Complex + compatible with this binding must have Block Revision + Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in + the MC control register region. + + reg: + items: + - description: + the first region is the command portal for the + this machine and must always be present + + - description: + the second region is the MC control registers. This + region may not be present in some scenarios, such + as in the device tree presented to a virtual machine. + + ranges: + description: | + A standard property. Defines the mapping between the child + MC address space and the parent system address space. + + The MC address space is defined by 3 components: + <region type> <offset hi> <offset lo> + + Valid values for region type are + 0x0 - MC portals + 0x1 - QBMAN portals + + "#address-cells": + const: 3 + + "#size-cells": + const: 1 + + iommu-map: + description: | + Maps an ICID to an IOMMU and associated iommu-specifier + data. + + The property is an arbitrary number of tuples of + (icid-base,iommu,iommu-base,length). + + Any ICID i in the interval [icid-base, icid-base + length) is + associated with the listed IOMMU, with the iommu-specifier + (i - icid-base + iommu-base). + + msi-map: + description: | + Maps an ICID to a GIC ITS and associated msi-specifier + data. + + The property is an arbitrary number of tuples of + (icid-base,gic-its,msi-base,length). + + Any ICID in the interval [icid-base, icid-base + length) is + associated with the listed GIC ITS, with the msi-specifier + (i - icid-base + msi-base). + + msi-parent: + deprecated: true + $ref: /schemas/types.yaml#/definitions/phandle + description: + Describes the MSI controller node handling message + interrupts for the MC. When there is no translation + between the ICID and deviceID this property can be used + to describe the MSI controller used by the devices on the + mc-bus. + The use of this property for mc-bus is deprecated. Please + use msi-map. + + dma-coherent: true + + dpmacs: + type: object + description: + The fsl-mc node may optionally have dpmac sub-nodes that describe + the relationship between the Ethernet MACs which belong to the MC + and the Ethernet PHYs on the system board. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^ethernet@[a-f0-9]+$': + $ref: /schemas/net/fsl,qoriq-mc-dpmac.yaml + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x0c000000 0x40>, /* MC portal base */ + <0x08340000 0x40000>; /* MC control reg */ + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x8 0x18000000 0x8000000>; + + /* define map for ICIDs 23-64 */ + iommu-map = <23 &smmu 23 41>; + /* define msi map for ICIDs 23-64 */ + msi-map = <23 &its 23 41>; + #address-cells = <3>; + #size-cells = <1>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + phy-handle = <&mdio0_phy0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/imx-iim.yaml b/Documentation/devicetree/bindings/nvmem/imx-iim.yaml index e9d9d8df4811..bb37d72c9eaa 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-iim.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-iim.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX IC Identification Module (IIM) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | This binding represents the IC Identification Module (IIM) found on diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml index be1314454bec..e21c06e9a741 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX On-Chip OTP Controller (OCOTP) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | This binding represents the on-chip eFuse OTP controller found on diff --git a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml index d9287be89877..95121dd6311c 100644 --- a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: On-Chip OTP Memory for Freescale i.MX23/i.MX28 maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: nvmem.yaml# diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml index 8bef9dfeba9a..ac0a35bf8648 100644 --- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX TPM PWM controller maintainers: - - Anson Huang <anson.huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | The TPM counter and period counter are shared between multiple diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml index 8f50e23ca8c9..a9d3a41ac5b9 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml @@ -8,7 +8,6 @@ title: Freescale MXS PWM controller maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <anson.huang@nxp.com> allOf: - $ref: pwm.yaml# diff --git a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt deleted file mode 100644 index 2a00e14e11e0..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt +++ /dev/null @@ -1,56 +0,0 @@ -QorIQ DPAA Buffer Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Portal - - Example - -BMan Portal Node - -Portals are memory mapped interfaces to BMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the BMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman-portal-<hardware revision>" - May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -EXAMPLE - -The example below shows a (P4080) BMan portals container/bus node with two portals - - bman-portals@ff4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4000000 0x200000>; - - bman-portal@0 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x100000 0x1000>; - interrupts = <105 2 0 0>; - }; - bman-portal@4000 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <107 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt deleted file mode 100644 index 48eed140765b..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt +++ /dev/null @@ -1,137 +0,0 @@ -QorIQ DPAA Buffer Manager Device Tree Bindings - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Node - - BMan Private Memory Node - - Example - -BMan Node - -The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). -BMan supports hardware allocation and deallocation of buffers belonging to pools -originally created by software with configurable depletion thresholds. This -binding covers the CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman" - May include "fsl,<SoC>-bman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The BMan revision information is located in the BMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,bman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this BMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -Devices connected to a BMan instance via Direct Connect Portals (DCP) must link -to the respective BMan instance - -- fsl,bman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the BMan instance - to which this device is connected via the DCP - -BMan Private Memory Node - -BMan requires a contiguous range of physical memory used for the backing store -for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as -a node under the /reserved-memory node. - -The BMan FBPR memory node must be named "bman-fbpr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,bman-fbpr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FBPR private memory: - - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to - 16 GiB - - The alignment must be a muliptle of the memory size - -The size of the FBPR must be chosen by observing the hardware features configured -via the Reset Configuration Word (RCW) and that are relevant to a specific board -(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, -etc.). The size configured in the DT must reflect the hardware capabilities and -not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a BMan FBPR dynamic allocation memory node - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-mem-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - }; - -The example below shows a (P4080) BMan CCSR-space node - - bportals: bman-portals@ff4000000 { - ... - }; - - crypto@300000 { - ... - fsl,bman = <&bman, 2>; - ... - }; - - bman: bman@31a000 { - compatible = "fsl,bman"; - reg = <0x31a000 0x1000>; - interrupts = <16 2 1 2>; - fsl,liodn = <0x17>; - fsl,bman-portals = <&bportals>; - memory-region = <&bman_fbpr>; - }; - - fman@400000 { - ... - fsl,bman = <&bman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml new file mode 100644 index 000000000000..53b07d4edc77 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Firmware Node + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This node defines a firmware binary that is embedded in the device tree, for + the purpose of passing the firmware from bootloader to the kernel, or from + the hypervisor to the guest. + + The firmware node itself contains the firmware binary contents, a compatible + property, and any firmware-specific properties. The node should be placed + inside a QE node that needs it. Doing so eliminates the need for a + fsl,firmware-phandle property. Other QE nodes that need the same firmware + should define an fsl,firmware-phandle property that points to the firmware node + in the first QE node. + + The fsl,firmware property can be specified in the DTS (possibly using incbin) + or can be inserted by the boot loader at boot time. + +properties: + compatible: + enum: + - fsl,qe-firmware + + fsl,firmware: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + A standard property. This property contains the firmware binary "blob". + +required: + - compatible + - fsl,firmware + +additionalProperties: false + +examples: + - | + qe-firmware { + compatible = "fsl,qe-firmware"; + fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml new file mode 100644 index 000000000000..8267ad00727b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Interrupt Controller (IC) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,qe-ic + + reg: + maxItems: 1 + + interrupts: + items: + - description: QE interrupt + - description: QE critical + - description: QE error + minItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml new file mode 100644 index 000000000000..cf0f38dbbe0d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Multi-User RAM (MURAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: Multi-User RAM (MURAM) + +properties: + compatible: + items: + - const: fsl,qe-muram + - const: fsl,cpm-muram + + ranges: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, slave] + + +patternProperties: + '^data\-only@[a-f0-9]+$': + type: object + properties: + compatible: + items: + - const: fsl,qe-muram-data + - const: fsl,cpm-muram-data + + reg: + maxItems: 1 + + required: + - compatible + - reg + + additionalProperties: false + +required: + - compatible + - ranges + +additionalProperties: false + +examples: + - | + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml new file mode 100644 index 000000000000..8e58ab58c063 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block (SI) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The SI manages the routing of eight TDM lines to the QE block serial drivers, + the MCC and the UCCs, for receive and transmit. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-si + - const: fsl,t1040-qe-si + - enum: + - fsl,t1040-qe-si + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml new file mode 100644 index 000000000000..cc4ed48d786c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + store the routing entries of SI + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-siram + - const: fsl,t1040-qe-siram + - const: fsl,t1040-qe-siram + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml new file mode 100644 index 000000000000..89cdf5e1d0a8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module (QE) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This represents qe module that is installed on PowerQUICC II Pro. + + NOTE: This is an interim binding; it should be updated to fit + in with the CPM binding later in this document. + + Basically, it is a bus of devices, that could act more or less + as a complete entity (UCC, USB etc ). All of them should be siblings on + the "root" qe node, using the common properties from there. + The description below applies to the qe of MPC8360 and + more nodes and properties would be extended in the future. + +properties: + compatible: + items: + - const: fsl,qe + - const: simple-bus + + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + model: + $ref: /schemas/types.yaml#/definitions/string + enum: [QE, CPM, CPM2] + + bus-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the clock frequency for QUICC Engine. + + fsl,qe-num-riscs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: define how many RISC engines the QE has. + + fsl,qe-snums: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 28 + description: + defining the array of serial number (SNUM) values for the virtual + threads. + + fsl,firmware-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + required only if there is no fsl,qe-firmware child node + + Points to a firmware node (see "QE Firmware Node" below) + that contains the firmware that should be uploaded for this QE. + The compatible property for the firmware node should say, + "fsl,qe-firmware". + + brg-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + the internal clock source frequency for baud-rate + generators in Hz. + + fsl,qe-num-snums: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: | + define how many serial number(SNUM) the QE can use + for the threads. Use fsl,qe-snums instead to not only specify the + number of snums, but also their values. + +patternProperties: + '^muram@[a-f0-9]+$': + $ref: fsl,qe-muram.yaml + + '^interrupt-controller@[a-f0-9]+$': + $ref: fsl,qe-ic.yaml + + '^si@[a-f0-9]+$': + $ref: fsl,qe-si.yaml + + '^siram@[a-f0-9]+$': + $ref: fsl,qe-siram.yaml + +required: + - compatible + - reg + - bus-frequency + +allOf: + - $ref: /schemas/simple-bus.yaml# + +unevaluatedProperties: false + +examples: + - | + qe-bus@e0100000 { + compatible = "fsl,qe", "simple-bus"; + reg = <0xe0100000 0x480>; + ranges = <0 0xe0100000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + brg-frequency = <0>; + bus-frequency = <0x179a7b00>; + fsl,qe-snums = /bits/ 8 < + 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d + 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 + 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 + 0xd8 0xd9 0xe8 0xe9>; + + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; + + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt deleted file mode 100644 index 05ec2a838c54..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ /dev/null @@ -1,178 +0,0 @@ -* Freescale QUICC Engine module (QE) -This represents qe module that is installed on PowerQUICC II Pro. - -NOTE: This is an interim binding; it should be updated to fit -in with the CPM binding later in this document. - -Basically, it is a bus of devices, that could act more or less -as a complete entity (UCC, USB etc ). All of them should be siblings on -the "root" qe node, using the common properties from there. -The description below applies to the qe of MPC8360 and -more nodes and properties would be extended in the future. - -i) Root QE device - -Required properties: -- compatible : should be "fsl,qe"; -- model : precise model of the QE, Can be "QE", "CPM", or "CPM2" -- reg : offset and length of the device registers. -- bus-frequency : the clock frequency for QUICC Engine. -- fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-snums: This property has to be specified as '/bits/ 8' value, - defining the array of serial number (SNUM) values for the virtual - threads. - -Optional properties: -- fsl,firmware-phandle: - Usage: required only if there is no fsl,qe-firmware child node - Value type: <phandle> - Definition: Points to a firmware node (see "QE Firmware Node" below) - that contains the firmware that should be uploaded for this QE. - The compatible property for the firmware node should say, - "fsl,qe-firmware". - -Recommended properties -- brg-frequency : the internal clock source frequency for baud-rate - generators in Hz. - -Deprecated properties -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use - for the threads. Use fsl,qe-snums instead to not only specify the - number of snums, but also their values. - -Example: - qe@e0100000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - compatible = "fsl,qe"; - ranges = <0 e0100000 00100000>; - reg = <e0100000 480>; - brg-frequency = <0>; - bus-frequency = <179A7B00>; - fsl,qe-snums = /bits/ 8 < - 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D - 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89 - 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9 - 0xD8 0xD9 0xE8 0xE9>; - } - -* Multi-User RAM (MURAM) - -Required properties: -- compatible : should be "fsl,qe-muram", "fsl,cpm-muram". -- mode : the could be "host" or "slave". -- ranges : Should be defined as specified in 1) to describe the - translation of MURAM addresses. -- data-only : sub-node which defines the address area under MURAM - bus that can be allocated as data/parameter - -Example: - - muram@10000 { - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0 00010000 0000c000>; - - data-only@0{ - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0 c000>; - }; - }; - -* Interrupt Controller (IC) - -Required properties: -- compatible : should be "fsl,qe-ic". -- reg : Address range of IC register set. -- interrupts : interrupts generated by the device. -- interrupt-controller : this device is a interrupt controller. - -Example: - - qeic: interrupt-controller@80 { - interrupt-controller; - compatible = "fsl,qe-ic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - interrupts = <95 2 0 0 94 2 0 0>; - }; - -* Serial Interface Block (SI) - -The SI manages the routing of eight TDM lines to the QE block serial drivers -, the MCC and the UCCs, for receive and transmit. - -Required properties: -- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain - "fsl,t1040-qe-si". -- reg : Address range of SI register set. - -Example: - - si1: si@700 { - compatible = "fsl,t1040-qe-si"; - reg = <0x700 0x80>; - }; - -* Serial Interface Block RAM(SIRAM) - -store the routing entries of SI - -Required properties: -- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain - "fsl,t1040-qe-siram". -- reg : Address range of SI RAM. - -Example: - - siram1: siram@1000 { - compatible = "fsl,t1040-qe-siram"; - reg = <0x1000 0x800>; - }; - -* QE Firmware Node - -This node defines a firmware binary that is embedded in the device tree, for -the purpose of passing the firmware from bootloader to the kernel, or from -the hypervisor to the guest. - -The firmware node itself contains the firmware binary contents, a compatible -property, and any firmware-specific properties. The node should be placed -inside a QE node that needs it. Doing so eliminates the need for a -fsl,firmware-phandle property. Other QE nodes that need the same firmware -should define an fsl,firmware-phandle property that points to the firmware node -in the first QE node. - -The fsl,firmware property can be specified in the DTS (possibly using incbin) -or can be inserted by the boot loader at boot time. - -Required properties: - - compatible - Usage: required - Value type: <string> - Definition: A standard property. Specify a string that indicates what - kind of firmware it is. For QE, this should be "fsl,qe-firmware". - - - fsl,firmware - Usage: required - Value type: <prop-encoded-array>, encoded as an array of bytes - Definition: A standard property. This property contains the firmware - binary "blob". - -Example: - qe1@e0080000 { - compatible = "fsl,qe"; - qe_firmware:qe-firmware { - compatible = "fsl,qe-firmware"; - fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; - }; - ... - }; - - qe2@e0090000 { - compatible = "fsl,qe"; - fsl,firmware-phandle = <&qe_firmware>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml new file mode 100644 index 000000000000..8dce75bebff9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + QorIQ DPAA Buffer Manager Portal + + Portals are memory mapped interfaces to BMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the BMan + +properties: + compatible: + oneOf: + - const: fsl,bman-portal + - items: + - enum: + - fsl,bman-portal-1.0.0 + - fsl,ls1043a-bmap-portal + - fsl,ls1046a-bmap-portal + - const: fsl,bman-portal + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman-portal@0 { + compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; + reg = <0x0 0x4000>, <0x100000 0x1000>; + interrupts = <105 IRQ_TYPE_EDGE_FALLING 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml new file mode 100644 index 000000000000..e6f468264b8d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Buffer Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). + BMan supports hardware allocation and deallocation of buffers belonging to + pools originally created by software with configurable depletion thresholds. + This binding covers the CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,bman + - items: + - enum: + - fsl,ls1043a-bman + - fsl,ls1046a-bman + - const: fsl,bman + + reg: + items: + - description: | + Registers region within the CCSR address space + + The BMan revision information is located in the BMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + memory-region: + minItems: 1 + maxItems: 2 + description: + List of phandles referencing the BMan private memory + nodes (described below). The bman-fqd node must be + first followed by bman-pfdr node. Only used on ARM + + Devices connected to a BMan instance via Direct Connect Portals (DCP) must link + to the respective BMan instance + + fsl,bman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,bman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman@31a000 { + compatible = "fsl,bman"; + reg = <0x31a000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 2>; + fsl,liodn = <0x17>; + fsl,bman-portals = <&bportals>; + memory-region = <&bman_fbpr>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml new file mode 100644 index 000000000000..31295be91013 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape Reset Registers Module + +maintainers: + - Frank Li + +description: + Reset Module includes chip reset, service processor control and Reset Control + Word (RCW) status. + +properties: + $nodename: + pattern: "^syscon@[0-9a-f]+$" + + compatible: + items: + - enum: + - fsl,ls1028a-reset + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + little-endian: true + + reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - reboot + +additionalProperties: false + +examples: + - | + syscon@1e60000 { + compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd"; + reg = <0x1e60000 0x10000>; + little-endian; + + reboot { + compatible = "syscon-reboot"; + offset = <0>; + mask = <0x02>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml new file mode 100644 index 000000000000..de0b4ae740ff --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-fqd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QMan Private Memory Nodes + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + QMan requires two contiguous range of physical memory used for the backing store + for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). + This memory is reserved/allocated as a node under the /reserved-memory node. + + BMan requires a contiguous range of physical memory used for the backing store + for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as + a node under the /reserved-memory node. + + The QMan FQD memory node must be named "qman-fqd" + The QMan PFDR memory node must be named "qman-pfdr" + The BMan FBPR memory node must be named "bman-fbpr" + + The following constraints are relevant to the FQD and PFDR private memory: + - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to + 1 GiB + - The alignment must be a muliptle of the memory size + + The size of the FQD and PFDP must be chosen by observing the hardware features + configured via the Reset Configuration Word (RCW) and that are relevant to a + specific board (e.g. number of MAC(s) pinned-out, number of offline/host command + FMan ports, etc.). The size configured in the DT must reflect the hardware + capabilities and not the specific needs of an application + + For additional details about reserved memory regions see + reserved-memory/reserved-memory.yaml in dtschema project. + +properties: + $nodename: + pattern: '^(qman-fqd|qman-pfdr|bman-fbpr)+$' + + compatible: + enum: + - fsl,qman-fqd + - fsl,qman-pfdr + - fsl,bman-fbpr + +required: + - compatible + +allOf: + - $ref: reserved-memory.yaml + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + qman-fqd { + compatible = "shared-dma-pool"; + size = <0 0x400000>; + alignment = <0 0x400000>; + no-map; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml new file mode 100644 index 000000000000..17016184143f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + Portals are memory mapped interfaces to QMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the QMan + +properties: + compatible: + oneOf: + - const: fsl,qman-portal + - items: + - enum: + - fsl,ls1043-qman-portal + - fsl,ls1046-qman-portal + - fsl,qman-portal-1.2.0 + - const: fsl,qman-portal + + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: See pamu.txt. Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN + (FLIODN) + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: See pamu.txt. + + fsl,qman-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: qman channel id. + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The hardware index of the channel. This can also be + determined by dividing any of the channel's 8 work queue + IDs by 8 + + In addition to these properties the qman-portals should have sub-nodes to + represent the HW devices/portals that are connected to the software portal + described here + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +patternProperties: + '^(fman0|fman1|pme|crypto)+$': + type: object + properties: + fsl,liodn: + description: See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + description: See pamu.txt, PAMU property used for dynamic LIODN assignment + + dev-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the particular hardware device that this + portal is connected to. + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman-portal@0 { + compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; + reg = <0 0x4000>, <0x100000 0x1000>; + interrupts = <104 IRQ_TYPE_EDGE_FALLING 0 0>; + fsl,liodn = <1 2>; + fsl,qman-channel-id = <0>; + + fman0 { + fsl,liodn = <0x21>; + dev-handle = <&fman0>; + }; + + fman1 { + fsl,liodn = <0xa1>; + dev-handle = <&fman1>; + }; + + crypto { + fsl,liodn = <0x41 0x66>; + dev-handle = <&crypto>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml new file mode 100644 index 000000000000..501f06e190c4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan + supports queuing and QoS scheduling of frames to CPUs, network interfaces and + DPAA logic modules, maintains packet ordering within flows. Besides providing + flow-level queuing, is also responsible for congestion management functions such + as RED/WRED, congestion notifications and tail discards. This binding covers the + CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,qman + - items: + - enum: + - fsl,ls1043a-qman + - fsl,ls1046a-qman + - const: fsl,qman + reg: + items: + - description: | + Registers region within the CCSR address space + + The QMan revision information is located in the QMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + fsl,qman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,qman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + + clocks: + maxItems: 1 + description: + Reference input clock. Its frequency is half of the platform clock + + memory-region: + maxItems: 2 + description: + List of phandles referencing the QMan private memory nodes (described + below). The qman-fqd node must be first followed by qman-pfdr node. + Only used on ARM Devices connected to a QMan instance via Direct Connect + Portals (DCP) must link to the respective QMan instance. + + fsl,qman: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of phandle and DCP index pairs, to the QMan instance + to which this device is connected via the DCP + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman: qman@318000 { + compatible = "fsl,qman"; + reg = <0x318000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 3>; + fsl,liodn = <0x16>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; + clocks = <&platform_pll 1>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt deleted file mode 100644 index 5a34f3ab7bea..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt +++ /dev/null @@ -1,134 +0,0 @@ -QorIQ DPAA Queue Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Portal - - Example - -QMan Portal Node - -Portals are memory mapped interfaces to QMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the QMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman-portal-<hardware revision>" - May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN - (FLIODN) - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- cell-index - Usage: Required - Value type: <u32> - Definition: The hardware index of the channel. This can also be - determined by dividing any of the channel's 8 work queue - IDs by 8 - -In addition to these properties the qman-portals should have sub-nodes to -represent the HW devices/portals that are connected to the software portal -described here - -The currently supported sub-nodes are: - * fman0 - * fman1 - * pme - * crypto - -These subnodes should have the following properties: - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - -- dev-handle - Usage: Required - Value type: <phandle> - Definition: The phandle to the particular hardware device that this - portal is connected to. - -EXAMPLE - -The example below shows a (P4080) QMan portals container/bus node with two portals - - qman-portals@ff4200000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4200000 0x200000>; - - qman-portal@0 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0 0x4000>, <0x100000 0x1000>; - interrupts = <104 2 0 0>; - fsl,liodn = <1 2>; - fsl,qman-channel-id = <0>; - - fman0 { - fsl,liodn = <0x21>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa1>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x41 0x66>; - dev-handle = <&crypto>; - }; - }; - qman-portal@4000 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <106 2 0 0>; - fsl,liodn = <3 4>; - cell-index = <1>; - - fman0 { - fsl,liodn = <0x22>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa2>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x42 0x67>; - dev-handle = <&crypto>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt deleted file mode 100644 index ee96afd2af72..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman.txt +++ /dev/null @@ -1,187 +0,0 @@ -QorIQ DPAA Queue Manager Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Node - - QMan Private Memory Nodes - - Example - -QMan Node - -The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan -supports queuing and QoS scheduling of frames to CPUs, network interfaces and -DPAA logic modules, maintains packet ordering within flows. Besides providing -flow-level queuing, is also responsible for congestion management functions such -as RED/WRED, congestion notifications and tail discards. This binding covers the -CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman" - May include "fsl,<SoC>-qman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The QMan revision information is located in the QMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,qman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this QMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- clocks - Usage: See clock-bindings.txt and qoriq-clock.txt - Value type: <prop-encoded-array> - Definition: Reference input clock. Its frequency is half of the - platform clock -- memory-regions - Usage: Required for ARM - Value type: <phandle array> - Definition: List of phandles referencing the QMan private memory - nodes (described below). The qman-fqd node must be - first followed by qman-pfdr node. Only used on ARM - -Devices connected to a QMan instance via Direct Connect Portals (DCP) must link -to the respective QMan instance - -- fsl,qman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the QMan instance - to which this device is connected via the DCP - -QMan Private Memory Nodes - -QMan requires two contiguous range of physical memory used for the backing store -for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). -This memory is reserved/allocated as a node under the /reserved-memory node. - -For additional details about reserved memory regions see reserved-memory.txt - -The QMan FQD memory node must be named "qman-fqd" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-fqd" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The QMan PFDR memory node must be named "qman-pfdr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-pfdr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FQD and PFDR private memory: - - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to - 1 GiB - - The alignment must be a muliptle of the memory size - -The size of the FQD and PFDP must be chosen by observing the hardware features -configured via the Reset Configuration Word (RCW) and that are relevant to a -specific board (e.g. number of MAC(s) pinned-out, number of offline/host command -FMan ports, etc.). The size configured in the DT must reflect the hardware -capabilities and not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - -The example below shows a (P4080) QMan CCSR-space node - - qportals: qman-portals@ff4200000 { - ... - }; - - clockgen: global-utilities@e1000 { - ... - sysclk: sysclk { - ... - }; - ... - platform_pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - ... - }; - - crypto@300000 { - ... - fsl,qman = <&qman, 2>; - ... - }; - - qman: qman@318000 { - compatible = "fsl,qman"; - reg = <0x318000 0x1000>; - interrupts = <16 2 1 3> - fsl,liodn = <0x16>; - fsl,qman-portals = <&qportals>; - memory-region = <&qman_fqd &qman_pfdr>; - clocks = <&platform_pll 1>; - }; - - fman@400000 { - ... - fsl,qman = <&qman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index 2ff174244795..ed1d4aa41b8c 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Low Power SPI (LPSPI) for i.MX maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: /schemas/spi/spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml index 808d987bd8d1..337560562337 100644 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml @@ -8,7 +8,6 @@ title: NXP i.MX Thermal maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <Anson.Huang@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index e7ddaa6c966e..bef0e95e7416 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8M Mini Thermal maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | i.MX8MM has TMU IP to allow temperature measurement, there are diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml index 1876fe9555d6..aa756dae512a 100644 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> $ref: thermal-sensor.yaml# diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index b6dd98d956f3..75b0e7c70b62 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -95,6 +95,7 @@ required: - compatible - reg - interrupts + - interrupt-names - clocks - clock-names - power-domains diff --git a/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml b/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml new file mode 100644 index 000000000000..62c6da8bab5a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sprd,sc9860-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 timer + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: + The Spreadtrum SC9860 platform provides 3 general-purpose timers. + These timers can support 32bit or 64bit counter, as well as supporting + period mode or one-shot mode, and they can be a wakeup source + during deep sleep. + +properties: + compatible: + enum: + - sprd,sc9860-timer + - sprd,sc9860-suspend-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: sprd,sc9860-timer + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + timer@40050000 { + compatible = "sprd,sc9860-timer"; + reg = <0 0x40050000 0 0x20>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_32k>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt b/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt deleted file mode 100644 index 6d97e7d0f6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt +++ /dev/null @@ -1,20 +0,0 @@ -Spreadtrum timers - -The Spreadtrum SC9860 platform provides 3 general-purpose timers. -These timers can support 32bit or 64bit counter, as well as supporting -period mode or one-shot mode, and they are can be wakeup source -during deep sleep. - -Required properties: -- compatible: should be "sprd,sc9860-timer" for SC9860 platform. -- reg: The register address of the timer device. -- interrupts: Should contain the interrupt for the timer device. -- clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock). - -Example: - timer@40050000 { - compatible = "sprd,sc9860-timer"; - reg = <0 0x40050000 0 0x20>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ext_32k>; - }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 03e290cb65c3..5d3dc952770d 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -364,6 +364,8 @@ properties: - sparkfun,qwiic-joystick # i2c serial eeprom (24cxx) - st,24c256 + # Sierra Wireless mangOH Green SPI IoT interface + - swir,mangoh-iotport-spi # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 # Temperature Monitoring and Fan Control diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index cd3680dc002f..25a5edeea164 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -46,11 +46,11 @@ properties: clocks: minItems: 7 - maxItems: 11 + maxItems: 9 clock-names: minItems: 7 - maxItems: 11 + maxItems: 9 dma-coherent: true @@ -217,16 +217,14 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 9 + maxItems: 9 clock-names: items: - - const: core_clk_src - const: core_clk - const: bus_clk - const: bus_aggr_clk - const: iface_clk - - const: core_clk_unipro_src - const: core_clk_unipro - const: core_clk_ice - const: ref_clk @@ -287,7 +285,7 @@ allOf: maxItems: 2 clocks: minItems: 7 - maxItems: 11 + maxItems: 9 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 181f0cc5b5bd..36b836d0620c 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX Watchdog Timer (WDT) Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml index 9c50766bf690..a09686b3030d 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: watchdog.yaml# diff --git a/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml b/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml new file mode 100644 index 000000000000..a88a27354505 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/img,pdc-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT) + +maintainers: + - Shresth Prasad <shresthprasad7@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - img,pdc-wdt + + reg: + maxItems: 1 + + clocks: + items: + - description: watchdog counter clock + - description: register interface clock + + clock-names: + items: + - const: wdt + - const: sys + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + watchdog@18102100 { + compatible = "img,pdc-wdt"; + reg = <0x18102100 0x100>; + clocks = <&pdc_wdt_clk>, <&sys_clk>; + clock-names = "wdt", "sys"; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt b/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt deleted file mode 100644 index b2fa11fd43de..000000000000 --- a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -*ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT) - -Required properties: -- compatible : Should be "img,pdc-wdt" -- reg : Should contain WDT registers location and length -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Should contain "wdt" and "sys"; the watchdog counter - clock and register interface clock respectively. -- interrupts : Should contain WDT interrupt - -Examples: - -watchdog@18102100 { - compatible = "img,pdc-wdt"; - reg = <0x18102100 0x100>; - clocks = <&pdc_wdt_clk>, <&sys_clk>; - clock-names = "wdt", "sys"; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst b/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst index 199647729251..32ee827a3a2c 100644 --- a/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst +++ b/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst @@ -339,7 +339,7 @@ Key functions include: a bind of the root DPRC to the DPRC driver The binding for the MC-bus device-tree node can be consulted at -*Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt*. +*Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml*. The sysfs bind/unbind interfaces for the MC-bus can be consulted at *Documentation/ABI/testing/sysfs-bus-fsl-mc*. diff --git a/MAINTAINERS b/MAINTAINERS index 08d5e7e8e408..8f4593ce9663 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9082,7 +9082,7 @@ M: Eddie James <eajames@linux.ibm.com> L: linux-i2c@vger.kernel.org L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/i2c/i2c-fsi.txt +F: Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml F: drivers/i2c/busses/i2c-fsi.c FSI-ATTACHED SPI DRIVER diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c index dda6092e6d3a..110104a936d9 100644 --- a/drivers/of/dynamic.c +++ b/drivers/of/dynamic.c @@ -984,7 +984,7 @@ EXPORT_SYMBOL_GPL(of_changeset_add_prop_string); int of_changeset_add_prop_string_array(struct of_changeset *ocs, struct device_node *np, const char *prop_name, - const char **str_array, size_t sz) + const char * const *str_array, size_t sz) { struct property prop; int i, ret; @@ -1047,3 +1047,28 @@ int of_changeset_add_prop_u32_array(struct of_changeset *ocs, return of_changeset_add_prop_helper(ocs, np, &prop); } EXPORT_SYMBOL_GPL(of_changeset_add_prop_u32_array); + +/** + * of_changeset_add_prop_bool - Add a boolean property (i.e. a property without + * any values) to a changeset. + * + * @ocs: changeset pointer + * @np: device node pointer + * @prop_name: name of the property to be added + * + * Create a boolean property and add it to a changeset. + * + * Return: 0 on success, a negative error value in case of an error. + */ +int of_changeset_add_prop_bool(struct of_changeset *ocs, struct device_node *np, + const char *prop_name) +{ + struct property prop; + + prop.name = (char *)prop_name; + prop.length = 0; + prop.value = NULL; + + return of_changeset_add_prop_helper(ocs, np, &prop); +} +EXPORT_SYMBOL_GPL(of_changeset_add_prop_bool); diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index a8a04f27915b..68103ad230ee 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -52,28 +52,7 @@ void __init of_fdt_limit_memory(int limit) int memory; int len; const void *val; - int nr_address_cells = OF_ROOT_NODE_ADDR_CELLS_DEFAULT; - int nr_size_cells = OF_ROOT_NODE_SIZE_CELLS_DEFAULT; - const __be32 *addr_prop; - const __be32 *size_prop; - int root_offset; - int cell_size; - - root_offset = fdt_path_offset(initial_boot_params, "/"); - if (root_offset < 0) - return; - - addr_prop = fdt_getprop(initial_boot_params, root_offset, - "#address-cells", NULL); - if (addr_prop) - nr_address_cells = fdt32_to_cpu(*addr_prop); - - size_prop = fdt_getprop(initial_boot_params, root_offset, - "#size-cells", NULL); - if (size_prop) - nr_size_cells = fdt32_to_cpu(*size_prop); - - cell_size = sizeof(uint32_t)*(nr_address_cells + nr_size_cells); + int cell_size = sizeof(uint32_t)*(dt_root_addr_cells + dt_root_size_cells); memory = fdt_path_offset(initial_boot_params, "/memory"); if (memory > 0) { @@ -1170,6 +1149,10 @@ bool __init early_init_dt_verify(void *params) initial_boot_params = params; of_fdt_crc32 = crc32_be(~0, initial_boot_params, fdt_totalsize(initial_boot_params)); + + /* Initialize {size,address}-cells info */ + early_init_dt_scan_root(); + return true; } @@ -1178,9 +1161,6 @@ void __init early_init_dt_scan_nodes(void) { int rc; - /* Initialize {size,address}-cells info */ - early_init_dt_scan_root(); - /* Retrieve various information from the /chosen node */ rc = early_init_dt_scan_chosen(boot_command_line); if (rc) diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 445ad13dab98..c830f346df45 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -917,6 +917,171 @@ static void __init of_unittest_changeset(void) #endif } +static void __init __maybe_unused changeset_check_string(struct device_node *np, + const char *prop_name, + const char *expected_str) +{ + const char *str; + int ret; + + ret = of_property_read_string(np, prop_name, &str); + if (unittest(ret == 0, "failed to read %s\n", prop_name)) + return; + + unittest(strcmp(str, expected_str) == 0, + "%s value mismatch (read '%s', exp '%s')\n", + prop_name, str, expected_str); +} + +static void __init __maybe_unused changeset_check_string_array(struct device_node *np, + const char *prop_name, + const char * const *expected_array, + unsigned int count) +{ + const char *str; + unsigned int i; + int ret; + int cnt; + + cnt = of_property_count_strings(np, prop_name); + if (unittest(cnt >= 0, "failed to get %s count\n", prop_name)) + return; + + if (unittest(cnt == count, + "%s count mismatch (read %d, exp %u)\n", + prop_name, cnt, count)) + return; + + for (i = 0; i < count; i++) { + ret = of_property_read_string_index(np, prop_name, i, &str); + if (unittest(ret == 0, "failed to read %s[%d]\n", prop_name, i)) + continue; + + unittest(strcmp(str, expected_array[i]) == 0, + "%s[%d] value mismatch (read '%s', exp '%s')\n", + prop_name, i, str, expected_array[i]); + } +} + +static void __init __maybe_unused changeset_check_u32(struct device_node *np, + const char *prop_name, + u32 expected_u32) +{ + u32 val32; + int ret; + + ret = of_property_read_u32(np, prop_name, &val32); + if (unittest(ret == 0, "failed to read %s\n", prop_name)) + return; + + unittest(val32 == expected_u32, + "%s value mismatch (read '%u', exp '%u')\n", + prop_name, val32, expected_u32); +} + +static void __init __maybe_unused changeset_check_u32_array(struct device_node *np, + const char *prop_name, + const u32 *expected_array, + unsigned int count) +{ + unsigned int i; + u32 val32; + int ret; + int cnt; + + cnt = of_property_count_u32_elems(np, prop_name); + if (unittest(cnt >= 0, "failed to get %s count\n", prop_name)) + return; + + if (unittest(cnt == count, + "%s count mismatch (read %d, exp %u)\n", + prop_name, cnt, count)) + return; + + for (i = 0; i < count; i++) { + ret = of_property_read_u32_index(np, prop_name, i, &val32); + if (unittest(ret == 0, "failed to read %s[%d]\n", prop_name, i)) + continue; + + unittest(val32 == expected_array[i], + "%s[%d] value mismatch (read '%u', exp '%u')\n", + prop_name, i, val32, expected_array[i]); + } +} + +static void __init __maybe_unused changeset_check_bool(struct device_node *np, + const char *prop_name) +{ + unittest(of_property_read_bool(np, prop_name), + "%s value mismatch (read 'false', exp 'true')\n", prop_name); +} + +static void __init of_unittest_changeset_prop(void) +{ +#ifdef CONFIG_OF_DYNAMIC + static const char * const str_array[] = { "abc", "defg", "hij" }; + static const u32 u32_array[] = { 123, 4567, 89, 10, 11 }; + struct device_node *nchangeset, *np; + struct of_changeset chgset; + int ret; + + nchangeset = of_find_node_by_path("/testcase-data/changeset"); + if (!nchangeset) { + pr_err("missing testcase data\n"); + return; + } + + of_changeset_init(&chgset); + + np = of_changeset_create_node(&chgset, nchangeset, "test-prop"); + if (unittest(np, "failed to create test-prop node\n")) + goto end_changeset_destroy; + + ret = of_changeset_add_prop_string(&chgset, np, "prop-string", "abcde"); + unittest(ret == 0, "failed to add prop-string\n"); + + ret = of_changeset_add_prop_string_array(&chgset, np, "prop-string-array", + str_array, ARRAY_SIZE(str_array)); + unittest(ret == 0, "failed to add prop-string-array\n"); + + ret = of_changeset_add_prop_u32(&chgset, np, "prop-u32", 1234); + unittest(ret == 0, "failed to add prop-u32\n"); + + ret = of_changeset_add_prop_u32_array(&chgset, np, "prop-u32-array", + u32_array, ARRAY_SIZE(u32_array)); + unittest(ret == 0, "failed to add prop-u32-array\n"); + + ret = of_changeset_add_prop_bool(&chgset, np, "prop-bool"); + unittest(ret == 0, "failed to add prop-bool\n"); + + of_node_put(np); + + ret = of_changeset_apply(&chgset); + if (unittest(ret == 0, "failed to apply changeset\n")) + goto end_changeset_destroy; + + np = of_find_node_by_path("/testcase-data/changeset/test-prop"); + if (unittest(np, "failed to find test-prop node\n")) + goto end_revert_changeset; + + changeset_check_string(np, "prop-string", "abcde"); + changeset_check_string_array(np, "prop-string-array", str_array, ARRAY_SIZE(str_array)); + changeset_check_u32(np, "prop-u32", 1234); + changeset_check_u32_array(np, "prop-u32-array", u32_array, ARRAY_SIZE(u32_array)); + changeset_check_bool(np, "prop-bool"); + + of_node_put(np); + +end_revert_changeset: + ret = of_changeset_revert(&chgset); + unittest(ret == 0, "failed to revert changeset\n"); + +end_changeset_destroy: + of_changeset_destroy(&chgset); + of_node_put(nchangeset); +#endif +} + static void __init of_unittest_dma_get_max_cpu_address(void) { struct device_node *np; @@ -4101,6 +4266,7 @@ static int __init of_unittest(void) of_unittest_property_string(); of_unittest_property_copy(); of_unittest_changeset(); + of_unittest_changeset_prop(); of_unittest_parse_interrupts(); of_unittest_parse_interrupts_extended(); of_unittest_dma_get_max_cpu_address(); diff --git a/drivers/pci/of_property.c b/drivers/pci/of_property.c index 03539e505372..5a0b98e69795 100644 --- a/drivers/pci/of_property.c +++ b/drivers/pci/of_property.c @@ -183,6 +183,26 @@ static int of_pci_prop_interrupts(struct pci_dev *pdev, return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin); } +static int of_pci_prop_intr_ctrl(struct pci_dev *pdev, struct of_changeset *ocs, + struct device_node *np) +{ + int ret; + u8 pin; + + ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); + if (ret != 0) + return ret; + + if (!pin) + return 0; + + ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1); + if (ret) + return ret; + + return of_changeset_add_prop_bool(ocs, np, "interrupt-controller"); +} + static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs, struct device_node *np) { @@ -336,6 +356,10 @@ int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, ret = of_pci_prop_intr_map(pdev, ocs, np); if (ret) return ret; + } else { + ret = of_pci_prop_intr_ctrl(pdev, ocs, np); + if (ret) + return ret; } ret = of_pci_prop_ranges(pdev, ocs, np); diff --git a/include/linux/of.h b/include/linux/of.h index a0bedd038a05..13cf7a43b473 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1639,7 +1639,7 @@ int of_changeset_add_prop_string(struct of_changeset *ocs, int of_changeset_add_prop_string_array(struct of_changeset *ocs, struct device_node *np, const char *prop_name, - const char **str_array, size_t sz); + const char * const *str_array, size_t sz); int of_changeset_add_prop_u32_array(struct of_changeset *ocs, struct device_node *np, const char *prop_name, @@ -1652,6 +1652,9 @@ static inline int of_changeset_add_prop_u32(struct of_changeset *ocs, return of_changeset_add_prop_u32_array(ocs, np, prop_name, &val, 1); } +int of_changeset_add_prop_bool(struct of_changeset *ocs, struct device_node *np, + const char *prop_name); + #else /* CONFIG_OF_DYNAMIC */ static inline int of_reconfig_notifier_register(struct notifier_block *nb) { diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 9f06f6aaf7fc..29da0dc9776d 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -407,8 +407,15 @@ cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) +DT_CHECK_CMD = $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) + +ifneq ($(CHECK_DTBS),) +quiet_cmd_fdtoverlay = DTOVLCH $@ + cmd_fdtoverlay = $(objtree)/scripts/dtc/fdtoverlay -o $@ -i $(real-prereqs) ; $(DT_CHECK_CMD) $@ || true +else quiet_cmd_fdtoverlay = DTOVL $@ cmd_fdtoverlay = $(objtree)/scripts/dtc/fdtoverlay -o $@ -i $(real-prereqs) +endif $(multi-dtb-y): FORCE $(call if_changed,fdtoverlay) @@ -421,7 +428,7 @@ DT_BINDING_DIR := Documentation/devicetree/bindings DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/processed-schema.json quiet_cmd_dtb = DTC_CHK $@ - cmd_dtb = $(cmd_dtc) ; $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ || true + cmd_dtb = $(cmd_dtc) ; $(DT_CHECK_CMD) $@ || true else quiet_cmd_dtb = $(quiet_cmd_dtc) cmd_dtb = $(cmd_dtc) diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c index 9f31d2607182..10fb63894369 100644 --- a/scripts/dtc/checks.c +++ b/scripts/dtc/checks.c @@ -31,7 +31,7 @@ typedef void (*check_fn)(struct check *c, struct dt_info *dti, struct node *node struct check { const char *name; check_fn fn; - void *data; + const void *data; bool warn, error; enum checkstatus status; bool inprogress; @@ -114,6 +114,7 @@ static inline void PRINTF(5, 6) check_msg(struct check *c, struct dt_info *dti, } fputs(str, stderr); + free(str); } #define FAIL(c, dti, node, ...) \ @@ -207,7 +208,7 @@ static void check_is_string(struct check *c, struct dt_info *dti, struct node *node) { struct property *prop; - char *propname = c->data; + const char *propname = c->data; prop = get_property(node, propname); if (!prop) @@ -226,7 +227,7 @@ static void check_is_string_list(struct check *c, struct dt_info *dti, { int rem, l; struct property *prop; - char *propname = c->data; + const char *propname = c->data; char *str; prop = get_property(node, propname); @@ -254,7 +255,7 @@ static void check_is_cell(struct check *c, struct dt_info *dti, struct node *node) { struct property *prop; - char *propname = c->data; + const char *propname = c->data; prop = get_property(node, propname); if (!prop) @@ -1078,10 +1079,11 @@ static void check_i2c_bus_reg(struct check *c, struct dt_info *dti, struct node /* Ignore I2C_OWN_SLAVE_ADDRESS */ reg &= ~I2C_OWN_SLAVE_ADDRESS; - if ((reg & I2C_TEN_BIT_ADDRESS) && ((reg & ~I2C_TEN_BIT_ADDRESS) > 0x3ff)) - FAIL_PROP(c, dti, node, prop, "I2C address must be less than 10-bits, got \"0x%x\"", + if (reg & I2C_TEN_BIT_ADDRESS) { + if ((reg & ~I2C_TEN_BIT_ADDRESS) > 0x3ff) + FAIL_PROP(c, dti, node, prop, "I2C address must be less than 10-bits, got \"0x%x\"", reg); - else if (reg > 0x7f) + } else if (reg > 0x7f) FAIL_PROP(c, dti, node, prop, "I2C address must be less than 7-bits, got \"0x%x\". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property", reg); } @@ -1108,7 +1110,7 @@ static void check_spi_bus_bridge(struct check *c, struct dt_info *dti, struct no for_each_child(node, child) { struct property *prop; for_each_property(child, prop) { - if (strprefixeq(prop->name, 4, "spi-")) { + if (strstarts(prop->name, "spi-")) { node->bus = &spi_bus; break; } @@ -1180,7 +1182,7 @@ static void check_unit_address_format(struct check *c, struct dt_info *dti, /* skip over 0x for next test */ unitname += 2; } - if (unitname[0] == '0' && isxdigit(unitname[1])) + if (unitname[0] == '0' && isxdigit((unsigned char)unitname[1])) FAIL(c, dti, node, "unit name should not have leading 0s"); } WARNING(unit_address_format, check_unit_address_format, NULL, @@ -1222,7 +1224,7 @@ static void check_avoid_unnecessary_addr_size(struct check *c, struct dt_info *d if (!node->parent || node->addr_cells < 0 || node->size_cells < 0) return; - if (get_property(node, "ranges") || !node->children) + if (get_property(node, "ranges") || get_property(node, "dma-ranges") || !node->children) return; for_each_child(node, child) { @@ -1232,7 +1234,7 @@ static void check_avoid_unnecessary_addr_size(struct check *c, struct dt_info *d } if (!has_reg) - FAIL(c, dti, node, "unnecessary #address-cells/#size-cells without \"ranges\" or child \"reg\" property"); + FAIL(c, dti, node, "unnecessary #address-cells/#size-cells without \"ranges\", \"dma-ranges\" or child \"reg\" property"); } WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size, NULL, &avoid_default_addr_size); @@ -1465,7 +1467,7 @@ static void check_provider_cells_property(struct check *c, struct dt_info *dti, struct node *node) { - struct provider *provider = c->data; + const struct provider *provider = c->data; struct property *prop; prop = get_property(node, provider->prop_name); @@ -1673,6 +1675,10 @@ static void check_interrupt_map(struct check *c, parent_cellsize += propval_cell(cellprop); cell += 1 + parent_cellsize; + if (cell > map_cells) + FAIL_PROP(c, dti, node, irq_map_prop, + "property size (%d) mismatch, expected %zu", + irq_map_prop->val.len, cell * sizeof(cell_t)); } } WARNING(interrupt_map, check_interrupt_map, NULL, &phandle_references, &addr_size_cells, &interrupt_provider); @@ -1765,6 +1771,11 @@ static void check_graph_nodes(struct check *c, struct dt_info *dti, get_property(child, "remote-endpoint"))) continue; + /* The root node cannot be a port */ + if (!node->parent) { + FAIL(c, dti, node, "root node contains endpoint node '%s', potentially misplaced remote-endpoint property", child->name); + continue; + } node->bus = &graph_port_bus; /* The parent of 'port' nodes can be either 'ports' or a device */ @@ -1778,31 +1789,6 @@ static void check_graph_nodes(struct check *c, struct dt_info *dti, } WARNING(graph_nodes, check_graph_nodes, NULL); -static void check_graph_child_address(struct check *c, struct dt_info *dti, - struct node *node) -{ - int cnt = 0; - struct node *child; - - if (node->bus != &graph_ports_bus && node->bus != &graph_port_bus) - return; - - for_each_child(node, child) { - struct property *prop = get_property(child, "reg"); - - /* No error if we have any non-zero unit address */ - if (prop && propval_cell(prop) != 0) - return; - - cnt++; - } - - if (cnt == 1 && node->addr_cells != -1) - FAIL(c, dti, node, "graph node has single child node '%s', #address-cells/#size-cells are not necessary", - node->children->name); -} -WARNING(graph_child_address, check_graph_child_address, NULL, &graph_nodes); - static void check_graph_reg(struct check *c, struct dt_info *dti, struct node *node) { @@ -1893,6 +1879,31 @@ static void check_graph_endpoint(struct check *c, struct dt_info *dti, } WARNING(graph_endpoint, check_graph_endpoint, NULL, &graph_nodes); +static void check_graph_child_address(struct check *c, struct dt_info *dti, + struct node *node) +{ + int cnt = 0; + struct node *child; + + if (node->bus != &graph_ports_bus && node->bus != &graph_port_bus) + return; + + for_each_child(node, child) { + struct property *prop = get_property(child, "reg"); + + /* No error if we have any non-zero unit address */ + if (prop && propval_cell(prop) != 0 ) + return; + + cnt++; + } + + if (cnt == 1 && node->addr_cells != -1) + FAIL(c, dti, node, "graph node has single child node '%s', #address-cells/#size-cells are not necessary", + node->children->name); +} +WARNING(graph_child_address, check_graph_child_address, NULL, &graph_nodes, &graph_port, &graph_endpoint); + static struct check *check_table[] = { &duplicate_node_names, &duplicate_property_names, &node_name_chars, &node_name_format, &property_name_chars, diff --git a/scripts/dtc/dtc-parser.y b/scripts/dtc/dtc-parser.y index bff1337ec266..4d5eece52624 100644 --- a/scripts/dtc/dtc-parser.y +++ b/scripts/dtc/dtc-parser.y @@ -284,14 +284,17 @@ propdef: DT_PROPNODENAME '=' propdata ';' { $$ = build_property($1, $3, &@$); + free($1); } | DT_PROPNODENAME ';' { $$ = build_property($1, empty_data, &@$); + free($1); } | DT_DEL_PROP DT_PROPNODENAME ';' { $$ = build_property_delete($2); + free($2); } | DT_LABEL propdef { @@ -570,10 +573,12 @@ subnode: DT_PROPNODENAME nodedef { $$ = name_node($2, $1); + free($1); } | DT_DEL_NODE DT_PROPNODENAME ';' { $$ = name_node(build_node_delete(&@$), $2); + free($2); } | DT_OMIT_NO_REF subnode { diff --git a/scripts/dtc/dtc.c b/scripts/dtc/dtc.c index bc786c543b7e..0655c2e2c362 100644 --- a/scripts/dtc/dtc.c +++ b/scripts/dtc/dtc.c @@ -47,7 +47,7 @@ static void fill_fullpaths(struct node *tree, const char *prefix) /* Usage related data. */ static const char usage_synopsis[] = "dtc [options] <input file>"; -static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:a:fb:i:H:sW:E:@AThv"; +static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:a:fb:i:H:sW:E:@LAThv"; static struct option const usage_long_opts[] = { {"quiet", no_argument, NULL, 'q'}, {"in-format", a_argument, NULL, 'I'}, @@ -67,6 +67,7 @@ static struct option const usage_long_opts[] = { {"warning", a_argument, NULL, 'W'}, {"error", a_argument, NULL, 'E'}, {"symbols", no_argument, NULL, '@'}, + {"local-fixups", no_argument, NULL, 'L'}, {"auto-alias", no_argument, NULL, 'A'}, {"annotate", no_argument, NULL, 'T'}, {"help", no_argument, NULL, 'h'}, @@ -104,6 +105,7 @@ static const char * const usage_opts_help[] = { "\n\tEnable/disable warnings (prefix with \"no-\")", "\n\tEnable/disable errors (prefix with \"no-\")", "\n\tEnable generation of symbols", + "\n\tPossibly generates a __local_fixups__ and a __fixups__ node at the root node", "\n\tEnable auto-alias of labels", "\n\tAnnotate output .dts with input source file and line (-T -T for more details)", "\n\tPrint this help and exit", @@ -252,6 +254,11 @@ int main(int argc, char *argv[]) case '@': generate_symbols = 1; break; + + case 'L': + generate_fixups = 1; + break; + case 'A': auto_label_aliases = 1; break; diff --git a/scripts/dtc/dtc.h b/scripts/dtc/dtc.h index 0a1f54991026..4c4aaca1fc41 100644 --- a/scripts/dtc/dtc.h +++ b/scripts/dtc/dtc.h @@ -260,16 +260,16 @@ struct node { void add_label(struct label **labels, char *label); void delete_labels(struct label **labels); -struct property *build_property(char *name, struct data val, +struct property *build_property(const char *name, struct data val, struct srcpos *srcpos); -struct property *build_property_delete(char *name); +struct property *build_property_delete(const char *name); struct property *chain_property(struct property *first, struct property *list); struct property *reverse_properties(struct property *first); struct node *build_node(struct property *proplist, struct node *children, struct srcpos *srcpos); struct node *build_node_delete(struct srcpos *srcpos); -struct node *name_node(struct node *node, char *name); +struct node *name_node(struct node *node, const char *name); struct node *omit_node_if_unused(struct node *node); struct node *reference_node(struct node *node); struct node *chain_node(struct node *first, struct node *list); @@ -336,9 +336,9 @@ struct dt_info *build_dt_info(unsigned int dtsflags, struct reserve_info *reservelist, struct node *tree, uint32_t boot_cpuid_phys); void sort_tree(struct dt_info *dti); -void generate_label_tree(struct dt_info *dti, char *name, bool allocph); -void generate_fixups_tree(struct dt_info *dti, char *name); -void generate_local_fixups_tree(struct dt_info *dti, char *name); +void generate_label_tree(struct dt_info *dti, const char *name, bool allocph); +void generate_fixups_tree(struct dt_info *dti, const char *name); +void generate_local_fixups_tree(struct dt_info *dti, const char *name); /* Checks */ diff --git a/scripts/dtc/fdtoverlay.c b/scripts/dtc/fdtoverlay.c index 5350af65679f..4eba0460f240 100644 --- a/scripts/dtc/fdtoverlay.c +++ b/scripts/dtc/fdtoverlay.c @@ -23,9 +23,7 @@ /* Usage related data. */ static const char usage_synopsis[] = "apply a number of overlays to a base blob\n" - " fdtoverlay <options> [<overlay.dtbo> [<overlay.dtbo>]]\n" - "\n" - USAGE_TYPE_MSG; + " fdtoverlay <options> [<overlay.dtbo> [<overlay.dtbo>]]"; static const char usage_short_opts[] = "i:o:v" USAGE_COMMON_SHORT_OPTS; static struct option const usage_long_opts[] = { {"input", required_argument, NULL, 'i'}, @@ -50,7 +48,7 @@ static void *apply_one(char *base, const char *overlay, size_t *buf_len, int ret; /* - * We take a copies first, because a a failed apply can trash + * We take a copies first, because a failed apply can trash * both the base blob and the overlay */ tmpo = xmalloc(fdt_totalsize(overlay)); diff --git a/scripts/dtc/flattree.c b/scripts/dtc/flattree.c index 95e43d32c3e6..1bcd8089c5b9 100644 --- a/scripts/dtc/flattree.c +++ b/scripts/dtc/flattree.c @@ -604,11 +604,11 @@ static void flat_realign(struct inbuf *inb, int align) die("Premature end of data parsing flat device tree\n"); } -static char *flat_read_string(struct inbuf *inb) +static const char *flat_read_string(struct inbuf *inb) { int len = 0; const char *p = inb->ptr; - char *str; + const char *str; do { if (p >= inb->limit) @@ -616,7 +616,7 @@ static char *flat_read_string(struct inbuf *inb) len++; } while ((*p++) != '\0'); - str = xstrdup(inb->ptr); + str = inb->ptr; inb->ptr += len; @@ -711,7 +711,7 @@ static struct reserve_info *flat_read_mem_reserve(struct inbuf *inb) } -static char *nodename_from_path(const char *ppath, const char *cpath) +static const char *nodename_from_path(const char *ppath, const char *cpath) { int plen; @@ -725,7 +725,7 @@ static char *nodename_from_path(const char *ppath, const char *cpath) if (!streq(ppath, "/")) plen++; - return xstrdup(cpath + plen); + return cpath + plen; } static struct node *unflatten_tree(struct inbuf *dtbuf, @@ -733,7 +733,7 @@ static struct node *unflatten_tree(struct inbuf *dtbuf, const char *parent_flatname, int flags) { struct node *node; - char *flatname; + const char *flatname; uint32_t val; node = build_node(NULL, NULL, NULL); @@ -741,9 +741,10 @@ static struct node *unflatten_tree(struct inbuf *dtbuf, flatname = flat_read_string(dtbuf); if (flags & FTF_FULLPATH) - node->name = nodename_from_path(parent_flatname, flatname); + node->name = xstrdup(nodename_from_path(parent_flatname, + flatname)); else - node->name = flatname; + node->name = xstrdup(flatname); do { struct property *prop; @@ -785,10 +786,6 @@ static struct node *unflatten_tree(struct inbuf *dtbuf, } } while (val != FDT_END_NODE); - if (node->name != flatname) { - free(flatname); - } - return node; } diff --git a/scripts/dtc/fstree.c b/scripts/dtc/fstree.c index 5e59594ab301..0f9a534bacdb 100644 --- a/scripts/dtc/fstree.c +++ b/scripts/dtc/fstree.c @@ -43,7 +43,7 @@ static struct node *read_fstree(const char *dirname) "WARNING: Cannot open %s: %s\n", tmpname, strerror(errno)); } else { - prop = build_property(xstrdup(de->d_name), + prop = build_property(de->d_name, data_copy_file(pfile, st.st_size), NULL); diff --git a/scripts/dtc/libfdt/fdt_overlay.c b/scripts/dtc/libfdt/fdt_overlay.c index 5c0c3981b89d..28b667ffc490 100644 --- a/scripts/dtc/libfdt/fdt_overlay.c +++ b/scripts/dtc/libfdt/fdt_overlay.c @@ -101,26 +101,22 @@ int fdt_overlay_target_offset(const void *fdt, const void *fdto, static int overlay_phandle_add_offset(void *fdt, int node, const char *name, uint32_t delta) { - const fdt32_t *val; - uint32_t adj_val; + fdt32_t *valp, val; int len; - val = fdt_getprop(fdt, node, name, &len); - if (!val) + valp = fdt_getprop_w(fdt, node, name, &len); + if (!valp) return len; - if (len != sizeof(*val)) + if (len != sizeof(val)) return -FDT_ERR_BADPHANDLE; - adj_val = fdt32_to_cpu(*val); - if ((adj_val + delta) < adj_val) - return -FDT_ERR_NOPHANDLES; - - adj_val += delta; - if (adj_val == (uint32_t)-1) + val = fdt32_ld(valp); + if (val + delta < val || val + delta == (uint32_t)-1) return -FDT_ERR_NOPHANDLES; - return fdt_setprop_inplace_u32(fdt, node, name, adj_val); + fdt32_st(valp, val + delta); + return 0; } /** @@ -213,8 +209,8 @@ static int overlay_update_local_node_references(void *fdto, fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) { const fdt32_t *fixup_val; - const char *tree_val; const char *name; + char *tree_val; int fixup_len; int tree_len; int i; @@ -228,7 +224,7 @@ static int overlay_update_local_node_references(void *fdto, return -FDT_ERR_BADOVERLAY; fixup_len /= sizeof(uint32_t); - tree_val = fdt_getprop(fdto, tree_node, name, &tree_len); + tree_val = fdt_getprop_w(fdto, tree_node, name, &tree_len); if (!tree_val) { if (tree_len == -FDT_ERR_NOTFOUND) return -FDT_ERR_BADOVERLAY; @@ -237,33 +233,15 @@ static int overlay_update_local_node_references(void *fdto, } for (i = 0; i < fixup_len; i++) { - fdt32_t adj_val; - uint32_t poffset; + fdt32_t *refp; - poffset = fdt32_to_cpu(fixup_val[i]); + refp = (fdt32_t *)(tree_val + fdt32_ld_(fixup_val + i)); /* - * phandles to fixup can be unaligned. - * - * Use a memcpy for the architectures that do - * not support unaligned accesses. + * phandles to fixup can be unaligned, so use + * fdt32_{ld,st}() to read/write them. */ - memcpy(&adj_val, tree_val + poffset, sizeof(adj_val)); - - adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta); - - ret = fdt_setprop_inplace_namelen_partial(fdto, - tree_node, - name, - strlen(name), - poffset, - &adj_val, - sizeof(adj_val)); - if (ret == -FDT_ERR_NOSPACE) - return -FDT_ERR_BADOVERLAY; - - if (ret) - return ret; + fdt32_st(refp, fdt32_ld(refp) + delta); } } @@ -337,7 +315,7 @@ static int overlay_update_local_references(void *fdto, uint32_t delta) * @name: Name of the property holding the phandle reference in the overlay * @name_len: number of name characters to consider * @poffset: Offset within the overlay property where the phandle is stored - * @label: Label of the node referenced by the phandle + * @phandle: Phandle referencing the node * * overlay_fixup_one_phandle() resolves an overlay phandle pointing to * a node in the base device tree. @@ -354,30 +332,14 @@ static int overlay_fixup_one_phandle(void *fdt, void *fdto, int symbols_off, const char *path, uint32_t path_len, const char *name, uint32_t name_len, - int poffset, const char *label) + int poffset, uint32_t phandle) { - const char *symbol_path; - uint32_t phandle; fdt32_t phandle_prop; - int symbol_off, fixup_off; - int prop_len; + int fixup_off; if (symbols_off < 0) return symbols_off; - symbol_path = fdt_getprop(fdt, symbols_off, label, - &prop_len); - if (!symbol_path) - return prop_len; - - symbol_off = fdt_path_offset(fdt, symbol_path); - if (symbol_off < 0) - return symbol_off; - - phandle = fdt_get_phandle(fdt, symbol_off); - if (!phandle) - return -FDT_ERR_NOTFOUND; - fixup_off = fdt_path_offset_namelen(fdto, path, path_len); if (fixup_off == -FDT_ERR_NOTFOUND) return -FDT_ERR_BADOVERLAY; @@ -416,6 +378,10 @@ static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, const char *value; const char *label; int len; + const char *symbol_path; + int prop_len; + int symbol_off; + uint32_t phandle; value = fdt_getprop_by_offset(fdto, property, &label, &len); @@ -426,6 +392,18 @@ static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, return len; } + symbol_path = fdt_getprop(fdt, symbols_off, label, &prop_len); + if (!symbol_path) + return prop_len; + + symbol_off = fdt_path_offset(fdt, symbol_path); + if (symbol_off < 0) + return symbol_off; + + phandle = fdt_get_phandle(fdt, symbol_off); + if (!phandle) + return -FDT_ERR_NOTFOUND; + do { const char *path, *name, *fixup_end; const char *fixup_str = value; @@ -467,7 +445,7 @@ static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off, path, path_len, name, name_len, - poffset, label); + poffset, phandle); if (ret) return ret; } while (len > 0); @@ -521,6 +499,255 @@ static int overlay_fixup_phandles(void *fdt, void *fdto) } /** + * overlay_adjust_local_conflicting_phandle: Changes a phandle value + * @fdto: Device tree overlay + * @node: The node the phandle is set for + * @fdt_phandle: The new value for the phandle + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_local_conflicting_phandle(void *fdto, int node, + uint32_t fdt_phandle) +{ + const fdt32_t *php; + int len, ret; + + php = fdt_getprop(fdto, node, "phandle", &len); + if (php && len == sizeof(*php)) { + ret = fdt_setprop_inplace_u32(fdto, node, "phandle", fdt_phandle); + if (ret) + return ret; + } + + php = fdt_getprop(fdto, node, "linux,phandle", &len); + if (php && len == sizeof(*php)) { + ret = fdt_setprop_inplace_u32(fdto, node, "linux,phandle", fdt_phandle); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_update_node_conflicting_references - Recursively replace phandle values + * @fdto: Device tree overlay blob + * @tree_node: Node to recurse into + * @fixup_node: Node offset of the matching local fixups node + * @fdt_phandle: Value to replace phandles with + * @fdto_phandle: Value to be replaced + * + * Replaces all phandles with value @fdto_phandle by @fdt_phandle. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_node_conflicting_references(void *fdto, int tree_node, + int fixup_node, + uint32_t fdt_phandle, + uint32_t fdto_phandle) +{ + int fixup_prop; + int fixup_child; + int ret; + + fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) { + const fdt32_t *fixup_val; + const char *name; + char *tree_val; + int fixup_len; + int tree_len; + int i; + + fixup_val = fdt_getprop_by_offset(fdto, fixup_prop, + &name, &fixup_len); + if (!fixup_val) + return fixup_len; + + if (fixup_len % sizeof(uint32_t)) + return -FDT_ERR_BADOVERLAY; + fixup_len /= sizeof(uint32_t); + + tree_val = fdt_getprop_w(fdto, tree_node, name, &tree_len); + if (!tree_val) { + if (tree_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + + return tree_len; + } + + for (i = 0; i < fixup_len; i++) { + fdt32_t *refp; + uint32_t valp; + + refp = (fdt32_t *)(tree_val + fdt32_ld_(fixup_val + i)); + valp = fdt32_ld(refp); + + if (valp == fdto_phandle) + fdt32_st(refp, fdt_phandle); + } + } + + fdt_for_each_subnode(fixup_child, fdto, fixup_node) { + const char *fixup_child_name = fdt_get_name(fdto, fixup_child, NULL); + int tree_child; + + tree_child = fdt_subnode_offset(fdto, tree_node, fixup_child_name); + + if (tree_child == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (tree_child < 0) + return tree_child; + + ret = overlay_update_node_conflicting_references(fdto, tree_child, + fixup_child, + fdt_phandle, + fdto_phandle); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_update_local_conflicting_references - Recursively replace phandle values + * @fdto: Device tree overlay blob + * @fdt_phandle: Value to replace phandles with + * @fdto_phandle: Value to be replaced + * + * Replaces all phandles with value @fdto_phandle by @fdt_phandle. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_conflicting_references(void *fdto, + uint32_t fdt_phandle, + uint32_t fdto_phandle) +{ + int fixups; + + fixups = fdt_path_offset(fdto, "/__local_fixups__"); + if (fixups == -FDT_ERR_NOTFOUND) + return 0; + if (fixups < 0) + return fixups; + + return overlay_update_node_conflicting_references(fdto, 0, fixups, + fdt_phandle, + fdto_phandle); +} + +/** + * overlay_prevent_phandle_overwrite_node - Helper function for overlay_prevent_phandle_overwrite + * @fdt: Base Device tree blob + * @fdtnode: Node in fdt that is checked for an overwrite + * @fdto: Device tree overlay blob + * @fdtonode: Node in fdto matching @fdtnode + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_prevent_phandle_overwrite_node(void *fdt, int fdtnode, + void *fdto, int fdtonode) +{ + uint32_t fdt_phandle, fdto_phandle; + int fdtochild; + + fdt_phandle = fdt_get_phandle(fdt, fdtnode); + fdto_phandle = fdt_get_phandle(fdto, fdtonode); + + if (fdt_phandle && fdto_phandle) { + int ret; + + ret = overlay_adjust_local_conflicting_phandle(fdto, fdtonode, + fdt_phandle); + if (ret) + return ret; + + ret = overlay_update_local_conflicting_references(fdto, + fdt_phandle, + fdto_phandle); + if (ret) + return ret; + } + + fdt_for_each_subnode(fdtochild, fdto, fdtonode) { + const char *name = fdt_get_name(fdto, fdtochild, NULL); + int fdtchild; + int ret; + + fdtchild = fdt_subnode_offset(fdt, fdtnode, name); + if (fdtchild == -FDT_ERR_NOTFOUND) + /* + * no further overwrites possible here as this node is + * new + */ + continue; + + ret = overlay_prevent_phandle_overwrite_node(fdt, fdtchild, + fdto, fdtochild); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_prevent_phandle_overwrite - Fixes overlay phandles to not overwrite base phandles + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * Checks recursively if applying fdto overwrites phandle values in the base + * dtb. When such a phandle is found, the fdto is changed to use the fdt's + * phandle value to not break references in the base. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_prevent_phandle_overwrite(void *fdt, void *fdto) +{ + int fragment; + + fdt_for_each_subnode(fragment, fdto, 0) { + int overlay; + int target; + int ret; + + overlay = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (overlay == -FDT_ERR_NOTFOUND) + continue; + + if (overlay < 0) + return overlay; + + target = fdt_overlay_target_offset(fdt, fdto, fragment, NULL); + if (target == -FDT_ERR_NOTFOUND) + /* + * The subtree doesn't exist in the base, so nothing + * will be overwritten. + */ + continue; + else if (target < 0) + return target; + + ret = overlay_prevent_phandle_overwrite_node(fdt, target, + fdto, overlay); + if (ret) + return ret; + } + + return 0; +} + +/** * overlay_apply_node - Merges a node into the base device tree * @fdt: Base Device Tree blob * @target: Node offset in the base device tree to apply the fragment to @@ -824,18 +1051,26 @@ int fdt_overlay_apply(void *fdt, void *fdto) if (ret) goto err; + /* Increase all phandles in the fdto by delta */ ret = overlay_adjust_local_phandles(fdto, delta); if (ret) goto err; + /* Adapt the phandle values in fdto to the above increase */ ret = overlay_update_local_references(fdto, delta); if (ret) goto err; + /* Update fdto's phandles using symbols from fdt */ ret = overlay_fixup_phandles(fdt, fdto); if (ret) goto err; + /* Don't overwrite phandles in fdt */ + ret = overlay_prevent_phandle_overwrite(fdt, fdto); + if (ret) + goto err; + ret = overlay_merge(fdt, fdto); if (ret) goto err; diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c index 9f6c551a22c2..b78c4e48f1cb 100644 --- a/scripts/dtc/libfdt/fdt_ro.c +++ b/scripts/dtc/libfdt/fdt_ro.c @@ -255,6 +255,9 @@ int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen) FDT_RO_PROBE(fdt); + if (!can_assume(VALID_INPUT) && namelen <= 0) + return -FDT_ERR_BADPATH; + /* see if we have an alias */ if (*path != '/') { const char *q = memchr(path, '/', end - p); @@ -522,16 +525,31 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) return fdt32_ld_(php); } +static const void *fdt_path_getprop_namelen(const void *fdt, const char *path, + const char *propname, int propnamelen, + int *lenp) +{ + int offset = fdt_path_offset(fdt, path); + + if (offset < 0) + return NULL; + + return fdt_getprop_namelen(fdt, offset, propname, propnamelen, lenp); +} + const char *fdt_get_alias_namelen(const void *fdt, const char *name, int namelen) { - int aliasoffset; + int len; + const char *alias; - aliasoffset = fdt_path_offset(fdt, "/aliases"); - if (aliasoffset < 0) + alias = fdt_path_getprop_namelen(fdt, "/aliases", name, namelen, &len); + + if (!can_assume(VALID_DTB) && + !(alias && len > 0 && alias[len - 1] == '\0' && *alias == '/')) return NULL; - return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL); + return alias; } const char *fdt_get_alias(const void *fdt, const char *name) @@ -539,6 +557,17 @@ const char *fdt_get_alias(const void *fdt, const char *name) return fdt_get_alias_namelen(fdt, name, strlen(name)); } +const char *fdt_get_symbol_namelen(const void *fdt, + const char *name, int namelen) +{ + return fdt_path_getprop_namelen(fdt, "/__symbols__", name, namelen, NULL); +} + +const char *fdt_get_symbol(const void *fdt, const char *name) +{ + return fdt_get_symbol_namelen(fdt, name, strlen(name)); +} + int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen) { int pdepth = 0, p = 0; diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h index 77ccff19911e..2d409d8e829b 100644 --- a/scripts/dtc/libfdt/libfdt.h +++ b/scripts/dtc/libfdt/libfdt.h @@ -524,10 +524,35 @@ int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); * level matching the given component, differentiated only by unit * address). * + * If the path is not absolute (i.e. does not begin with '/'), the + * first component is treated as an alias. That is, the property by + * that name is looked up in the /aliases node, and the value of that + * property used in place of that first component. + * + * For example, for this small fragment + * + * / { + * aliases { + * i2c2 = &foo; // RHS compiles to "/soc@0/i2c@30a40000/eeprom@52" + * }; + * soc@0 { + * foo: i2c@30a40000 { + * bar: eeprom@52 { + * }; + * }; + * }; + * }; + * + * these would be equivalent: + * + * /soc@0/i2c@30a40000/eeprom@52 + * i2c2/eeprom@52 + * * returns: * structure block offset of the node with the requested path (>=0), on * success - * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_BADPATH, given path does not begin with '/' and the first + * component is not a valid alias * -FDT_ERR_NOTFOUND, if the requested node does not exist * -FDT_ERR_BADMAGIC, * -FDT_ERR_BADVERSION, @@ -870,6 +895,42 @@ const char *fdt_get_alias_namelen(const void *fdt, const char *fdt_get_alias(const void *fdt, const char *name); /** + * fdt_get_symbol_namelen - get symbol based on substring + * @fdt: pointer to the device tree blob + * @name: name of the symbol to look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_symbol(), but only examine the first @namelen + * characters of @name for matching the symbol name. + * + * Return: a pointer to the expansion of the symbol named @name, if it exists, + * NULL otherwise + */ +#ifndef SWIG /* Not available in Python */ +const char *fdt_get_symbol_namelen(const void *fdt, + const char *name, int namelen); +#endif + +/** + * fdt_get_symbol - retrieve the path referenced by a given symbol + * @fdt: pointer to the device tree blob + * @name: name of the symbol to look up + * + * fdt_get_symbol() retrieves the value of a given symbol. That is, + * the value of the property named @name in the node + * /__symbols__. Such a node exists only for a device tree blob that + * has been compiled with the -@ dtc option. Each property corresponds + * to a label appearing in the device tree source, with the name of + * the property being the label and the value being the full path of + * the node it is attached to. + * + * returns: + * a pointer to the expansion of the symbol named 'name', if it exists + * NULL, if the given symbol or the /__symbols__ node does not exist + */ +const char *fdt_get_symbol(const void *fdt, const char *name); + +/** * fdt_get_path - determine the full path of a node * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose path to find @@ -1450,7 +1511,7 @@ int fdt_nop_node(void *fdt, int nodeoffset); * fdt_create_with_flags() begins the process of creating a new fdt with * the sequential write interface. * - * fdt creation process must end with fdt_finished() to produce a valid fdt. + * fdt creation process must end with fdt_finish() to produce a valid fdt. * * returns: * 0, on success @@ -1968,7 +2029,7 @@ static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, * address and size) to the value of the named property in the given * node, or creates a new property with that value if it does not * already exist. - * If "name" is not specified, a default "reg" is used. + * * Cell sizes are determined by parent's #address-cells and #size-cells. * * This function may insert data into the blob, and will therefore diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c index f46a098d5ada..49f723002f85 100644 --- a/scripts/dtc/livetree.c +++ b/scripts/dtc/livetree.c @@ -36,27 +36,27 @@ void delete_labels(struct label **labels) label->deleted = 1; } -struct property *build_property(char *name, struct data val, +struct property *build_property(const char *name, struct data val, struct srcpos *srcpos) { struct property *new = xmalloc(sizeof(*new)); memset(new, 0, sizeof(*new)); - new->name = name; + new->name = xstrdup(name); new->val = val; new->srcpos = srcpos_copy(srcpos); return new; } -struct property *build_property_delete(char *name) +struct property *build_property_delete(const char *name) { struct property *new = xmalloc(sizeof(*new)); memset(new, 0, sizeof(*new)); - new->name = name; + new->name = xstrdup(name); new->deleted = 1; return new; @@ -116,11 +116,11 @@ struct node *build_node_delete(struct srcpos *srcpos) return new; } -struct node *name_node(struct node *node, char *name) +struct node *name_node(struct node *node, const char *name) { assert(node->name == NULL); - node->name = name; + node->name = xstrdup(name); return node; } @@ -250,6 +250,7 @@ struct node * add_orphan_node(struct node *dt, struct node *new_node, char *ref) name_node(new_node, "__overlay__"); node = build_node(p, new_node, NULL); name_node(node, name); + free(name); add_child(dt, node); return dt; @@ -440,7 +441,7 @@ cell_t propval_cell(struct property *prop) cell_t propval_cell_n(struct property *prop, unsigned int n) { - assert(prop->val.len / sizeof(cell_t) >= n); + assert(prop->val.len / sizeof(cell_t) > n); return fdt32_to_cpu(*((fdt32_t *)prop->val.val + n)); } @@ -616,10 +617,25 @@ struct node *get_node_by_ref(struct node *tree, const char *ref) return target; } +static void add_phandle_property(struct node *node, + const char *name, int format) +{ + struct data d; + + if (!(phandle_format & format)) + return; + if (get_property(node, name)) + return; + + d = data_add_marker(empty_data, TYPE_UINT32, NULL); + d = data_append_cell(d, node->phandle); + + add_property(node, build_property(name, d, NULL)); +} + cell_t get_node_phandle(struct node *root, struct node *node) { static cell_t phandle = 1; /* FIXME: ick, static local */ - struct data d = empty_data; if (phandle_is_valid(node->phandle)) return node->phandle; @@ -629,16 +645,8 @@ cell_t get_node_phandle(struct node *root, struct node *node) node->phandle = phandle; - d = data_add_marker(d, TYPE_UINT32, NULL); - d = data_append_cell(d, phandle); - - if (!get_property(node, "linux,phandle") - && (phandle_format & PHANDLE_LEGACY)) - add_property(node, build_property("linux,phandle", d, NULL)); - - if (!get_property(node, "phandle") - && (phandle_format & PHANDLE_EPAPR)) - add_property(node, build_property("phandle", d, NULL)); + add_phandle_property(node, "linux,phandle", PHANDLE_LEGACY); + add_phandle_property(node, "phandle", PHANDLE_EPAPR); /* If the node *does* have a phandle property, we must * be dealing with a self-referencing phandle, which will be @@ -808,18 +816,18 @@ void sort_tree(struct dt_info *dti) } /* utility helper to avoid code duplication */ -static struct node *build_and_name_child_node(struct node *parent, char *name) +static struct node *build_and_name_child_node(struct node *parent, const char *name) { struct node *node; node = build_node(NULL, NULL, NULL); - name_node(node, xstrdup(name)); + name_node(node, name); add_child(parent, node); return node; } -static struct node *build_root_node(struct node *dt, char *name) +static struct node *build_root_node(struct node *dt, const char *name) { struct node *an; @@ -1040,7 +1048,7 @@ static void generate_local_fixups_tree_internal(struct dt_info *dti, generate_local_fixups_tree_internal(dti, lfn, c); } -void generate_label_tree(struct dt_info *dti, char *name, bool allocph) +void generate_label_tree(struct dt_info *dti, const char *name, bool allocph) { if (!any_label_tree(dti, dti->dt)) return; @@ -1048,7 +1056,7 @@ void generate_label_tree(struct dt_info *dti, char *name, bool allocph) dti->dt, allocph); } -void generate_fixups_tree(struct dt_info *dti, char *name) +void generate_fixups_tree(struct dt_info *dti, const char *name) { if (!any_fixup_tree(dti, dti->dt)) return; @@ -1056,7 +1064,7 @@ void generate_fixups_tree(struct dt_info *dti, char *name) dti->dt); } -void generate_local_fixups_tree(struct dt_info *dti, char *name) +void generate_local_fixups_tree(struct dt_info *dti, const char *name) { if (!any_local_fixup_tree(dti, dti->dt)) return; diff --git a/scripts/dtc/srcpos.c b/scripts/dtc/srcpos.c index 4fdb22a019bd..8e4d18a90b47 100644 --- a/scripts/dtc/srcpos.c +++ b/scripts/dtc/srcpos.c @@ -3,7 +3,9 @@ * Copyright 2007 Jon Loeliger, Freescale Semiconductor, Inc. */ +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif #include <stdio.h> @@ -311,8 +313,8 @@ srcpos_string(struct srcpos *pos) static char * srcpos_string_comment(struct srcpos *pos, bool first_line, int level) { - char *pos_str, *fname, *first, *rest; - bool fresh_fname = false; + char *pos_str, *fresh_fname = NULL, *first, *rest; + const char *fname; if (!pos) { if (level > 1) { @@ -330,9 +332,9 @@ srcpos_string_comment(struct srcpos *pos, bool first_line, int level) else if (level > 1) fname = pos->file->name; else { - fname = shorten_to_initial_path(pos->file->name); - if (fname) - fresh_fname = true; + fresh_fname = shorten_to_initial_path(pos->file->name); + if (fresh_fname) + fname = fresh_fname; else fname = pos->file->name; } @@ -346,7 +348,7 @@ srcpos_string_comment(struct srcpos *pos, bool first_line, int level) first_line ? pos->first_line : pos->last_line); if (fresh_fname) - free(fname); + free(fresh_fname); if (pos->next != NULL) { rest = srcpos_string_comment(pos->next, first_line, level); diff --git a/scripts/dtc/treesource.c b/scripts/dtc/treesource.c index 33fedee82d58..ae15839ba6a5 100644 --- a/scripts/dtc/treesource.c +++ b/scripts/dtc/treesource.c @@ -139,6 +139,28 @@ static const char *delim_end[] = { [TYPE_STRING] = "", }; +static void add_string_markers(struct property *prop) +{ + int l, len = prop->val.len; + const char *p = prop->val.val; + + for (l = strlen(p) + 1; l < len; l += strlen(p + l) + 1) { + struct marker *m, **nextp; + + m = xmalloc(sizeof(*m)); + m->offset = l; + m->type = TYPE_STRING; + m->ref = NULL; + m->next = NULL; + + /* Find the end of the markerlist */ + nextp = &prop->val.markers; + while (*nextp) + nextp = &((*nextp)->next); + *nextp = m; + } +} + static enum markertype guess_value_type(struct property *prop) { int len = prop->val.len; @@ -164,6 +186,8 @@ static enum markertype guess_value_type(struct property *prop) if ((p[len-1] == '\0') && (nnotstring == 0) && (nnul <= (len-nnul)) && (nnotstringlbl == 0)) { + if (nnul > 1) + add_string_markers(prop); return TYPE_STRING; } else if (((len % sizeof(cell_t)) == 0) && (nnotcelllbl == 0)) { return TYPE_UINT32; @@ -241,6 +265,8 @@ static void write_propval(FILE *f, struct property *prop) } else { write_propval_int(f, p, chunk_len, 4); } + if (data_len > chunk_len) + fputc(' ', f); break; case TYPE_UINT64: write_propval_int(f, p, chunk_len, 8); diff --git a/scripts/dtc/util.h b/scripts/dtc/util.h index 9d38edee9736..b448cd79efd3 100644 --- a/scripts/dtc/util.h +++ b/scripts/dtc/util.h @@ -13,7 +13,9 @@ */ #ifdef __GNUC__ -#if __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) +#ifdef __MINGW_PRINTF_FORMAT +#define PRINTF(i, j) __attribute__((format (__MINGW_PRINTF_FORMAT, i, j))) +#elif __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) #define PRINTF(i, j) __attribute__((format (gnu_printf, i, j))) #else #define PRINTF(i, j) __attribute__((format (printf, i, j))) @@ -65,7 +67,7 @@ extern char *xstrndup(const char *s, size_t len); extern int PRINTF(2, 3) xasprintf(char **strp, const char *fmt, ...); extern int PRINTF(2, 3) xasprintf_append(char **strp, const char *fmt, ...); -extern int xavsprintf_append(char **strp, const char *fmt, va_list ap); +extern int PRINTF(2, 0) xavsprintf_append(char **strp, const char *fmt, va_list ap); extern char *join_path(const char *path, const char *name); /** diff --git a/scripts/dtc/version_gen.h b/scripts/dtc/version_gen.h index 99614ec1a289..4c5e17639d2b 100644 --- a/scripts/dtc/version_gen.h +++ b/scripts/dtc/version_gen.h @@ -1 +1 @@ -#define DTC_VERSION "DTC 1.6.1-gabbd523b" +#define DTC_VERSION "DTC 1.7.0-g1df7b047" |