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| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-06-30 10:18:59 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-08-20 18:10:58 +0200 |
| commit | 89d98ca0367b687562fc8c23b0985e667ae5be9e (patch) | |
| tree | 7a872a985edde3e80c26acdab22cc55d4aa33e03 | |
| parent | c5cee0cabb809617c5e275666f9e0fba184a20fd (diff) | |
| download | linux-stable-89d98ca0367b687562fc8c23b0985e667ae5be9e.tar.gz linux-stable-89d98ca0367b687562fc8c23b0985e667ae5be9e.tar.bz2 linux-stable-89d98ca0367b687562fc8c23b0985e667ae5be9e.zip | |
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
commit 3770821fa360525e6c726cd562a2438a0aa5d566 upstream.
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 8059a8d3ea36..31b77f71313f 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS), /* i2s */ COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, |