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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2017-03-14 18:13:26 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 16:30:08 +0000 |
| commit | cb567e79fa504575cb97fb2f866d2040ed1c92e7 (patch) | |
| tree | 0c97432063ddd4632d894f69ae49577af12e577f | |
| parent | c8c3798d2369e4285da44b244638eafe446a8f8a (diff) | |
| download | linux-stable-cb567e79fa504575cb97fb2f866d2040ed1c92e7.tar.gz linux-stable-cb567e79fa504575cb97fb2f866d2040ed1c92e7.tar.bz2 linux-stable-cb567e79fa504575cb97fb2f866d2040ed1c92e7.zip | |
arm64: v8.3: Support for complex number instructions
ARM v8.3 adds support for new instructions to aid floating-point
multiplication and addition of complex numbers. Expose the support
via HWCAP and MRS emulation
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 2 | ||||
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 1 | ||||
| -rw-r--r-- | arch/arm64/include/uapi/asm/hwcap.h | 1 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 1 |
5 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index 5b279dcee9c6..0ce0a4021aa4 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -174,6 +174,8 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| + | FCMA | [19-16] | y | + |--------------------------------------------------| | JSCVT | [15-12] | y | x--------------------------------------------------x diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cbb314389a5b..69af995c9b76 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -157,6 +157,7 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64isar1 */ +#define ID_AA64ISAR1_FCMA_SHIFT 16 #define ID_AA64ISAR1_JSCVT_SHIFT 12 /* id_aa64pfr0 */ diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 391a876f055d..85841a469cda 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -33,5 +33,6 @@ #define HWCAP_CPUID (1 << 11) #define HWCAP_ASIMDRDM (1 << 12) #define HWCAP_JSCVT (1 << 13) +#define HWCAP_FCMA (1 << 14) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3085d0e595c7..3ce8b18a1ab5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -98,6 +98,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -894,6 +895,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 32776597e4e6..4a43c6abb422 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -66,6 +66,7 @@ static const char *const hwcap_str[] = { "cpuid", "asimdrdm", "jscvt", + "fcma", NULL }; |