diff options
| author | Daniel Thompson <daniel.thompson@linaro.org> | 2014-05-23 16:01:43 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2014-05-26 12:53:40 +1000 |
| commit | 4cbe1bfa27dcc8e757c723f27e5a8e8b5fc32117 (patch) | |
| tree | 5a31eb5614a8f5562031f4be00de30e59520e97c /Documentation/EDID/1024x768.S | |
| parent | 9a6594fc5241ad96cff727a134f336b1f1eaa0f7 (diff) | |
| download | linux-stable-4cbe1bfa27dcc8e757c723f27e5a8e8b5fc32117.tar.gz linux-stable-4cbe1bfa27dcc8e757c723f27e5a8e8b5fc32117.tar.bz2 linux-stable-4cbe1bfa27dcc8e757c723f27e5a8e8b5fc32117.zip | |
drm: Add 800x600 (SVGA) screen resolution to the built-in EDIDs
The 800x600 (SVGA) screen resolution was lacking in the set of
built-in selectable EDID screen resolutions that can be used to
repair misbehaving monitor firmware.
This patch adds the related data set and expands the documentation.
Note that the SVGA bit occupies a different byte to all the existing
users of the established timing bits forcing a rework of the
ESTABLISHED_TIMINGS_BITS macro.
Tested new EDID on an aged (and misbehaving) industrial LCD panel;
existing EDIDs still pass edid-decode's checksum checks.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: David Airlie <airlied@linux.ie>
Cc: Carsten Emde <C.Emde@osadl.org>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'Documentation/EDID/1024x768.S')
| -rw-r--r-- | Documentation/EDID/1024x768.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/EDID/1024x768.S b/Documentation/EDID/1024x768.S index 4b486fe31b32..6f3e4b75e49e 100644 --- a/Documentation/EDID/1024x768.S +++ b/Documentation/EDID/1024x768.S @@ -36,7 +36,7 @@ #define DPI 72 #define VFREQ 60 /* Hz */ #define TIMING_NAME "Linux XGA" -#define ESTABLISHED_TIMINGS_BITS 0x08 /* Bit 3 -> 1024x768 @60 Hz */ +#define ESTABLISHED_TIMING2_BITS 0x08 /* Bit 3 -> 1024x768 @60 Hz */ #define HSYNC_POL 0 #define VSYNC_POL 0 #define CRC 0x55 |